David Robert Wallace Barr

APRON: a cellular processor array simulation and hardware design tool

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

A Control System for a Cellular Processor Array

Presented in this paper is a system that controls the SCAMP-3 cellular processor array vision chip, and provides an interface between it and a host system. This system can be used in real-time image processing, or computer vision applications. The system includes a sequencer for issuing instructions to the array processor, a configurable analogue interface and read-out circuitry, a system controller, which enables system operation and communication with the host, and a suite of software components, which include libraries, simulator, compiler and user interface. The presented hardware is a stand-alone vision system, which can be used in the development of PC-based or embedded applications

Implementation of multi-layer leaky integrator networks on a cellular processor array

We present an application of a massively parallel processor array VLSI circuit to the implementation of neural networks in complex architectural arrangements. The work was motivated by existing biologically plausible models of a set of sub-cortical nuclei -the basal ganglia. The model includes 5 layers, each consisting of 16384 leaky integrator neurons, with inter-layer synaptic weights forming various one-to-one and diffuse connectivity patterns. The architecture of the SIMD processor array allows all the neurons per layer to be updated simultaneously. The performance of the processor array chip in simulating the model is compared with the original model being executed on a computer workstation. It is demonstrated that in this application the chip outperforms the workstation by five orders of magnitude in terms of computational performance and seven orders of magnitude in terms of energy efficiency, providing a high-speed, low-power, compact hardware platform for possible embedded robotic applications.

Low power high-performance smart camera system based on SCAMP vision sensor

Vision sensors based upon pixel-parallel cellular processor arrays offer the unique opportunity to realise high-performance, flexible, low power image processing systems. By virtue of processing on the focal-plane, the energy-demanding requirement to digitize a captured frames raw pixel data is reduced, with returned data constituting only that which is salient. We describe a stand-alone vision system incorporating a SCAMP-3 vision chip, an FPGA and an ARM Cortex-M3 microcontroller. SCAMP integrated circuits operate as SIMD computers; each pixel incorporating a compact but powerful analogue processor and local memory, with all operations occurring in parallel over the 128x128 array. Algorithms are developed to operate natively upon the focal-plane as far as possible, with additional serial and higher-level operations occurring on the microcontroller. The power consumption of the system is algorithm-dependent. An algorithm developed for loiterer detection at 8fps has been shown to consume an average power of 5.5mW, with a more complex object tracking and counting system consuming 29mW.

Metachronal waves in cellular automata:Cilia-like manipulation in actuator arrays

Paramecium is covered by cilia. It uses the cilia to swim and transport food particles to its mouth. The cilia are synchronised into a collective action by propagating membrane potential and mechanical properties of their underlying membrane and the liquid phase environment. The cilia inspired us to design and manufacture a hardware prototype of a massively parallel actuator array, emulated membrane potentials via a discrete excitable medium controller and mechanical properties based on vibrating motors. The discrete excitable medium is a two-dimensional array of finite automata, where each automaton, or a cell, updates its state depending on states of its closest neighbours. A local interaction between the automata lead to emergence of propagating patterns, waves and gliders. The excitable medium is interfaced with an array of actuators. Patterns travelling on an automaton array manifest patterns of actuation travelling along the array of actuators. In computer models and laboratory experiments with hardware prototypes we imitate transportation of food towards mouth pore of the Paramecium. The hardware actuator arrays proposed could in future replace simple manipulators in demanding micro-scale application.

Mixed signal SIMD cellular processor array vision chip operating at 30,000 fps

A prototype vision chip has been designed that incorporates a 20 × 64 array of processing elements on a 31μm pitch. Each processor element includes 14 bits of digital memory in addition to 7 analogue registers. Digital operands include NOR and NOT with operations of diffusion, subtraction, inversion and squaring available in the analogue domain. The cells of the array can be configured as an asynchronous propagation network allowing operations such as flood filling to occur with times of ~1μs across the array. Exploiting this feature allows the chip to recognise the difference between closed and open shapes at 30,000 frames per second. The chip is fabricated in 0.18μm CMOS technology.

Demonstration of a low power image processing system using a SCAMP3 vision chip

A low power vision system has been developed incorporating the SCAMP3 pixel-parallel processor array vision chip. A test algorithm to detect loitering targets has shown an average power consumption of <6mW analysing 128×128 images at 8 frames per second.

A cellular processor array simulation and hardware prototyping tool

We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software is used to explore algorithms that are designed for CPAs, neuromorphic arrays, multi-layer neural networks and vision chips. The software (APRON) uses a highly optimised core combined with a flexible compiler to provide the user with tools for the prototyping of new array hardware and the emulation of existing devices. We show that software processor arrays can operate at impressive speeds, with high numerical accuracy. APRON can be configured to use additional processing hardware if necessary, and can even be used as the graphical user interface for new or existing CPA systems.

Demonstration of real-time image processing on the SCAMP-3 vision system

Vision system based on a cellular processor array integrated circuit is presented. The system includes the SCAMP-3 vision chip, control and interface circuits, and software development environment enabling code simulation, compilation and debugging. Execution of a number of low-level image processing algorithms in real-time is demonstrated.

Locating high speed multiple objects using a SCAMP-5 vision-chip

Presented in this paper is a demonstration system that uses a low-power SCAMP-5 256×256 vision-chip to locate and count multiple objects moving at high speed along arbitrary trajectories. The hardware consists of a SCAMP-5 IC, its power supply system and a Xilinx Spartan3 controller. At 100,000fps, the SCAMP-5 chip can locate and readout the coordinates of a single closed-shaped object amongst clutter. At 25,000fps, the IC can readout the coordinates of 5 objects.