Fook-Luen Heng

A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation

In this paper we propose a novel VLSI artwork modification technique based on the concept of a minimum layoutperturbation. Layouts are designed so that minimum design rules must be satisfied. Often layout processes such as custom layout methodologies and design rule migration activities introduce design rule violations in layouts. A minimum layout perturbation defines a minimum cost change to a layout, such that the resulting layout satisfies all design rules. We formulate the minimum perturbation cost with the objective of preserving as much as possible the geometric and topological features of the original layout. The proposed minimum perturbation problem formulation is transformed into a linear programming problem with special structure. We exploit the structure of the problem to propose efficient algorithms that solve the problem. We also propose and implement a practical graph-based simplex algorithm, which we compare to a commercially available linear programming package, resulting in more than 40X performance improvements in some cases. Finally, the proposed methods have been implemented and used in real life problems, for example in the technology migration of data path macros and a 30O-cell gate array library.

Toward through-process layout quality metrics

Quality of a layout has the most direct impact in the manufacturability of a design. Traditionally, layout quality is ensured in the first order by design rules, i.e. if a layout is free of design rules violation, it is a good layout. It is assumed such a layout will be fabricated to specification. Moreover, a design rule clean layout also ensures the electrical performance of the circuit it represents. There are other layout quality measures, e.g. random defects yield of a layout is modeled by critical area, systematic defects yield is sometime measured by a weighted score of recommended design rules. All the traditional layout quality measures are computed with drawn layout shapes. In the advent of low K1 lithography and the increasing variability of process technologies beyond 90nm, nominal layout quality measures need to be revisited. Traditionally, nominal electrical properties such as L-eff and W-eff are extracted from drawn layout, and the corner cases are estimated with worst case process conditions. Most of these parameters are layout pattern dependent. As a matter of fact, they can be systematic through process and can have large impact in the modeling of circuit parameters [1]. In this paper, we investigate a through process layout quality measure, in which we extract through process electrical parameters from simulated through process resist contours. We showed a mechanism to compute a statistical model that predicts through process electrical parameters from the process parameter variation. We demonstrated that such computation is practical.

Toward a systematic-variation aware timing methodology

Variability of circuit performance is becoming a very important issue for ultra-deep sub-micron technology. Gate length variation has the most direct impact on circuit performance. Since many factors contribute to the variability of gate length, recent studies have modeled the variability using Gaussian distributions. In reality, the through-pitch and through-focus variations of gate length are systematic. In this paper, we propose a timing methodology which takes these systematic variations into account and we show that it can reduce the timing uncertainty by up to 40%.

Backend CAD flows for "restrictive design rules"

To meet challenges of deep-subwavelength technologies (particularly 130 nm and following), lithography has come to rely increasingly on data processes such as shape fill, optical proximity correction, and RETs like altPSM. For emerging technologies (65 nm and following) the computation cost and complexity of these techniques are themselves becoming bottlenecks in the design-silicon flow. This has motivated the recent calls for restrictive design rules such as fixed width/pitch/orientation of gate-forming polysilicon features. We have been exploring how design might take advantage of these restrictions, and present some preliminary ideas for how we might reduce the computational cost throughout the back end of the design flow through the post-tapeout data processes while improving quality of results: the reliability of OPC/RET algorithms and the accuracy of models of manufactured products. We also believe that the underlying technology, including simulation and analysis, may be applicable to a variety of approaches to design for manufacturability (DFM).

Application of automated design migration to alternating phase shift mask design

The use of phase shifted mask (PSM) has been demonstrated to be a powerful resolution enhancement technique (RET) for the printing of features at dimensions below the exposure wavelength in deep submicron technologies. Its implementation in physical design has introduced non-conventional design ground rules, which impact the traditional layout migration process and designers productivity. In this panel discussion paper, we propose a solution to extend the traditional constraint-based layout migration and legalization approach. The solution has been demonstrated to be very effective in practice.

Technology migration technique for designs with strong RET-driven layout restrictions

Restrictive design rules (RDRs) have been introduced as a simplified layout optimization method to better enable resolution enhancement techniques in ultra-deep submicron designs (16). In this paper, we study the technology migration problem for designs with strong RET-driven layout restrictions, i.e., RDR constraints, which require devices (gates) to be placed on a coarse pitch and in a single orientation. In particular, we study the legalization problem with on-pitch constraints for devices with an objective of minimum layout perturbation. The problem can be formulated as an integer linear programming (ILP) problem with a set of stringent integer constraints, and it can be approximated as a mixed integer linear programming (MILP) problem. Instead of using an MILP solver to solve it, we propose a two-stage method --- first the target on-pitch positions for gates are computed and second the original problem is relaxed to a linear programming problem. Library cell layouts designed in a technology with conventional ground rules have been migrated successfully to a technology with RDRs using our approach.

Yield estimation of SRAM circuits using "Virtual SRAM Fab"

Static Random Access Memories (SRAMs) are key components of modern VLSI designs and a major bottleneck to technology scaling as they use the smallest size devices with high sensitivity to manufacturing details. Analysis performed at the “schematic” level can be deceiving as it ignores the interdependence between the implementation layout and the resulting electrical performance. We present a computational framework, referred to as “Virtual SRAM Fab”, for analyzing and estimating pre-Si SRAM array manufacturing yield considering both lithographic and electrical variations. The framework is being demonstrated for SRAM design/optimization in 45nm nodes and currently being used for both 32nm and 22nm technology nodes. The application and merit of the framework are illustrated using two different SRAM cells in a 45nm PD/SOI technology, which have been designed for similar stability/performance, but exhibit different parametric yields due to layout/lithographic variations. We also demonstrate the application of Virtual SRAM Fab for prediction of layout-induced imbalance in an 8T cell, which is a popular candidate for SRAM implementation in 32–22nm technology nodes.

Merits of cellwise model-based OPC

One of the most compute intensive dataprep operations for 90nm PC level is the model-based optical proximity correction (MBOPC). The running time and output data size are growing unacceptably, particularly for ASICs and designs containing large macros built out of library cells (books). The reason for this growth is that the region-of-interest for MBOPC is approximately 600nm, which means that most library cells “see” interactions with adjacent books in the same row and also in adjacent rows. In this paper, we investigate the merits of doing cellwise MBOPC. In its simplest form, the approach is to perform dataprep for each cell once per cell definition rather than once per placement. By inspection, this will reduce the computation time and output data size by a factor of P/D, where P is the number of book placements (100s to millions) and D is the number of book definitions. Our preliminary finding indicates that there is negligible difference between nominal CD for cellwise corrected cells and chipwise corrected cells. We will present our finding in terms of average CD and contact coverage, as well as runtime reduction.

A platform for the next generation of smarter energy applications

A number of key technological, social, and business disruptions will drive a new generation of smarter energy applications. The disruptions include the following: 1) large sensor deployments, resulting in a huge increase in data volumes and variety, 2) a move toward clean energy and intermittent renewable energy sources, and 3) a move to highly distributed energy resources. To enable resilient and efficient power delivery, with these disruptions, will require a host of new applications that analyze large amounts and varieties of data in the context of the connected grid and perform analysis, visualization, and control in real-time with very low latency. In this paper, we present a set of capabilities that enable such applications, and a software and hardware platform that combines these capabilities to enable rapid development of a wide array of high-performance and analytics-rich applications. These capabilities include: 1) high-performance time-series ingestion, 2) a flexible data model that spans multiple contexts, 3) high-performance, in-memory analysis of time-varying, hierarchical graphs, 4) data service for co-presenting real-time and static spatiotemporal data for real-time web-based visualization, and 5) a seamless combination of event-based and service-oriented programming models.

HAMS: A Memory-Efficient Representation of Power Grids Using Hierarchical and Multi-Scenario Graphs

Advanced analytical applications that will enable the smart grid need to analyze the connectivity of the power grid under multiple different operating scenarios, taking into account time-varying topology of the grid. This paper proposes a highly memory-efficient representation of the power grid that enables efficient construction of multiple topological and operational states in memory for high-performance graph analysis. The proposed representation exploits repeating patterns in the grid and uses a hierarchical graph as the core model. Time-varying topology and operational conditions are modeled as mapping functions on this hierarchical graph, so as to avoid construction of multiple graphs to represent multiple topologies. The efficiency and performance of the proposed representation is demonstrated on a large real-world distribution electrical grid.