Alexios N. Birbas

Investigation of 10-Gb/s RSOA-Based Upstream Transmission in WDM-PONs Utilizing Optical Filtering and Electronic Equalization

Enhanced upstream transmission at 10 Gb/s using a low-bandwidth reflective semiconductor optical amplifier is demonstrated and discussed for extended wavelength- division-multiplexing passive-optical-network applications. Significant improvement in terms of transmission performance is achieved with the use of electronic equalization and optimum filter offset placed at the receiver (optical line terminal) end only. According to filtering detuning, an analytical discussion is presented, explaining the bandwidth enhancement achieved with the proposed technique. The experimental studies consider the benefits of the electronic feed-forward and decision-feedback equalization as well as the required optimum offset optical filtering characteristics.

10 Gb/s full-duplex bidirectional transmission with RSOA-based ONU using detuned optical filtering and decision feedback equalization

Full-duplex bidirectional transmission at 10 Gb/s is demonstrated for extended wavelength division multiplexed passive optical network (WDM-PON) applications, achieving transmission distances up to 25 km of standard single mode fiber (SSMF) when using a low-bandwidth (approximately 1.2 GHz) reflective semiconductor optical amplifier (RSOA) for signal re-modulation at the optical network unit (ONU). The system is assisted by optimum offset filtering at the optical line terminal (OLT)-receiver and the performance is further improved with the use of decision-feedback equalization (DFE). Chromatic dispersion (CD) and Rayleigh Backscattering (RB) effects are considered and analyzed.

Design Characteristics for a Full-Duplex IM/IM Bidirectional Transmission at 10 Gb/s Using Low Bandwidth RSOA

In this paper, the optimum design characteristics and the transmission performance limits of an intensity modulation full-duplex bidirectional transmission system at 10 Gb/s are experimentally studied and presented for application in next-generation-extended wavelength-division-multiplexed passive optical networks. A low-bandwidth (~1.2 GHz) reflective semiconductor optical amplifier (RSOA) is utilized at the optical network unit (ONU) site of the system. Its remodulation properties and performance are examined for both continuous wave and modulated downstream signal, stemming from the optical line terminal (OLT). The techniques adopted to optimize performance are: 1) the use of detuned optical filtering at the OLT receiver that takes advantage of the RSOA chirp and 2) the use of decision feedback equalization (DFE). The extinction ratio of the downstream signal and the driving operation point of the RSOA are examined experimentally in order to find the optimum conditions for the bidirectional transmission. Moreover, the impact of patterning effects in the performance of the system is evaluated. Finally, the additional performance improvement that is achieved with the use of DFE technique is shown.

Hardware/Software Co-Design of Complex Embedded Systems: An Approach Using Efficient Process Models, Multiple Formalism Specification and Validation via Co-Simulation

This paper presents a hardware/software co-design approachwhere different specification languages can be used in parallel, allowingeffective system co-modeling. The proposed methodology introduces a processmodel that extends the traditional spiral model so as to reflect the designneeds of modern embedded systems. The methodology is supported by an advancedtoolset that allows co-modeling and co-simulation using SDL, Statecharts andMATRIXX, and interactive hardware/software partitioning. The effectivenessof the proposed approach is exhibited through two applicati on examples: thedesign of a car window lift mechanism, and the design of a MAC layer protocolfor wireless ATM networks.

A compact hybrid-multiplexed potentiostat for real-time electrochemical biosensing applications.

The architecture and design of a compact, multichannel, hybrid-multiplexed potentiostat for performing electrochemical measurements on continuously-biased electrode arrays is presented. The proposed architecture utilises a combination of sequential and parallel measurements, to enable high performance whilst keeping the system low-cost and compact. The accuracy of the signal readout is maintained by following a special multiplexing approach, which ensures the continuous biasing of all the working electrodes of an array. After sampling the results, a digital calibration technique factors out errors from component inaccuracies. A prototype printed circuit board (PCB) was designed and built using off-the-shelf components for the real-time measurement of the amperometric signal of 48 electrodes. The operation and performance of the PCB was evaluated and characterised through a wide range of testing conditions, where it exhibited high linearity (R(2)>0.999) and a resolution of 400pA. The effectiveness of the proposed multiplexing scheme is demonstrated through electrochemical tests using KCl and [Fe(CN)6](3-) in KCl solutions. The applicability of the prototype multichannel potentiostat is also demonstrated using real biosensors, which were applied to the detection of IgA antibodies.

Performance Improvement of Low-Cost 2.5-Gb/s Rated DML Sources Operated at 10 Gb/s

The transmission performance improvement of low-cost conventional directly modulated laser (DML) sources, fabricated for operation at 2.5 Gb/s but modulated at 10 Gb/s is presented and experimentally demonstrated. Performance improvement is achieved by electronic feed-forward and decision-feedback equalization as well as offset optical filtering at the receiver end. Experimental studies consider both transient and adiabatic chirp dominated DML sources. The transmission improvement is evaluated in terms of required optical signal-to-noise ratio (OSNR) for bit-error-rate values of 10-9 versus transmission length over uncompensated links of standard single-mode fiber (SSMF). Additionally, the optimum filter position is examined in combination with equalization and in terms of OSNR versus detuning from the center wavelength.

An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division

An asynchronous A/D Converter architecture based on a binary tree structure is presented in this paper. Two alternative design strategies are presented that lead either to a high mismatch immunity ADC that requires a light calibration logic (area: 0.123mm^2, power: 72mW) or a faster, tinier and even lower power ADC (area: 0.21mm^2, power: 25mW) with lower mismatch immunity that needs a slightly more complicated calibration logic. Both alternative ADC design strategies require at least one or two orders of magnitude lower area than any known approach and a remarkable low power consumption without sacrificing speed. The designed A/D Converter can operate with a configurable resolution of either 4, 8, or 12-bits. Moreover, 6 quaternary digits or three 16-level outputs are also available from the intermediate nodes of the binary tree, for applications that require multi-valued communication lines. Simulation results prove that the peak conversion rate of the high mismatch immunity A/D design alternative exceeds 300, 230 and 225MS/s for 4, 8 and 12-bit resolution, respectively, while the peak conversion rate of the faster design alternative is higher than 500, 440 and 420MS/s for 4, 8 and 12-bit resolution, respectively. An appropriate sample/hold and voltage to current conversion architecture has been developed along with an intelligent output latching technique that improve the achieved signal to noise and distortion ratio by up to 7dB. Moreover, an appropriate calibration method that extends the temperature operating range and compensates for the component mismatches is presented. The ultra low area and power consumption of the developed ADC architecture favours its employment in sensor networks while these features make its use attractive as a building block in time interleaved parallel ADCs for the achievement of ultra high speed conversion.

Fully Integrated Differential Distributed VCO in 0.35-

We present a fully integrated differential distributed voltage-controlled oscillator implemented in a 0.35-mum SiGe BiCMOS technology. The delay variation by a positive feedback tuning technique, adopted from the ring oscillators, is demonstrated as a fine-tuning alternative, which results to an approximately 420-MHz tuning range. The phase noise is -98 dBc/Hz at 1-MHz offset from the 14.25-GHz carrier. An integrated output buffer isolates the oscillator from the measurement equipment. The measured output power is -17.5 dBm and the overall power consumption of the chip is 138.1 mW employing two power supplies of 3.2 and 4.2 V, respectively

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Capacitive sensors have profoundly found their way in everyday life. Devices and instrumentation ranging from specialty equipment to smartphones all employ in one way or the other a capacitive sensor and its associated readout circuit, making the latter ubiquitious. We present a capacitive readout system that automatically adapts its range to the unknown measured capacitance, thereby extending its functional input range, as well as its application and instrumentation compatibility. The proposed system achieves a constant resolution for a range of input capacitance up to 690 pF.

SiGe BiCMOS Technology

Abstract Hardware–software co-design is the cornerstone in the design of complex systems that involve both hardware and software. This paper presents a co-design approach where the co-simulation between hardware and software takes place early enough in the design cycle. The proposed platform is based on the extension of existing instruction set processor simulators in order to encapsulate hardware block description in the required and adequate accuracy level. The simplicity of the proposed technique as well as the use of homogeneous simulation environment, leads to a co-simulation alternative that is easy to implement and use. The applicability of the co-simulation environment developed is exhibited through the design and co-simulation, at various abstraction layers, of a telecommunication application. The latter, is based on the MAC layer and the RF-IF part of the Physical layer of the DECT protocol stack.