Nikos Petrellis

Target Localization Utilizing the Success Rate in Infrared Pattern Recognition

The architecture of an indoor target localization system employing a small number of infrared-emitting diodes and sensors is presented in this paper. The properties of infrared light and magnetic fields have already been exploited for position localization in distances of several centimeters. Ultrasonic waves and laser light can be used for longer distance estimation if the system is capable of accurately measuring the time of flight of the reflected signals. The proposed approach intends to cover a distance of several meters without requiring high accuracy measurements and sensors of increased precision. The digital infrared patterns that are transmitted from a constant position are recognized by a pair of sensors mounted on the moving target, with varying success rate depending on the distance and the angular displacement from the transmitter. Processing the success rate instead of the analogue signal intensity requires low-cost digital microcontroller systems of moderate precision and computational power. Moreover, longer distances can be covered since attenuated, noisy, or scrambled patterns are also important for the position estimation in the proposed approach. A proper modeling of the pattern recognition success rate is presented in order to estimate distances of several meters with an adjustable estimation error. The use of multiple infrared pattern transmitting devices results in extension of the area covered and a reduction of the estimation error due to additional crosschecks that may be accomplished. The area covered can be increased by a factor between 20% and 100% depending on the allowed range overlapping of the transmitting devices. The potential topology of these devices is also discussed and analyzed. The presented system can be used in several virtual reality and robotics applications

An ultra low area asynchronous combo 4/8/12-bit/quaternary A/D converter based on integer division

An asynchronous A/D Converter architecture based on a binary tree structure is presented in this paper. Two alternative design strategies are presented that lead either to a high mismatch immunity ADC that requires a light calibration logic (area: 0.123mm^2, power: 72mW) or a faster, tinier and even lower power ADC (area: 0.21mm^2, power: 25mW) with lower mismatch immunity that needs a slightly more complicated calibration logic. Both alternative ADC design strategies require at least one or two orders of magnitude lower area than any known approach and a remarkable low power consumption without sacrificing speed. The designed A/D Converter can operate with a configurable resolution of either 4, 8, or 12-bits. Moreover, 6 quaternary digits or three 16-level outputs are also available from the intermediate nodes of the binary tree, for applications that require multi-valued communication lines. Simulation results prove that the peak conversion rate of the high mismatch immunity A/D design alternative exceeds 300, 230 and 225MS/s for 4, 8 and 12-bit resolution, respectively, while the peak conversion rate of the faster design alternative is higher than 500, 440 and 420MS/s for 4, 8 and 12-bit resolution, respectively. An appropriate sample/hold and voltage to current conversion architecture has been developed along with an intelligent output latching technique that improve the achieved signal to noise and distortion ratio by up to 7dB. Moreover, an appropriate calibration method that extends the temperature operating range and compensates for the component mismatches is presented. The ultra low area and power consumption of the developed ADC architecture favours its employment in sensor networks while these features make its use attractive as a building block in time interleaved parallel ADCs for the achievement of ultra high speed conversion.

Using future position restriction rules for stabilizing the results of a noise-sensitive indoor localization system

The testing and evaluation of a low cost system capable of estimating the position of a moving target within an extendible indoor area with low error is presented. Based on a recently developed system architecture, which makes use of a noise-sensitive indoor localization system made up of ir sensors, the position estimation error is based on comparing the number of the digital ir patterns received at the moving target with the expected one. To overcome the problem of instant noise that appears despite the effective system shielding, we employ a number of rules that take into consideration the previous position estimations. These rules are based on the fact that the speed of the target is always limited and its track is smooth most of the time. The test for the rules was made by running a series of experiments on the sensors system, and as a result, we verified that the maximum absolute error in the experimental results is approximately equal to the grid node distance. Moreover, the noise restrictions of the system were tested and recognized, allowing direct measurement of relevant parameters.

Compensating for moderate effective throughput at the desktop

This article presents the design and development of a networking system architecture targeted to support high-speed TCP/IP communication over ATM. The discussed architecture has been developed in the form of an integrated system which incorporates state-of-the-art software and hardware subsystems, and an OC-12c ATM adapter (622 Mb/s). Moreover, the design of this embedded system has been based on the Chorus real-time operating system, which, in turn, hosts an accelerated TCP/IP protocol stack over ATM. Furthermore, the embedded system board has been developed according to the PCI specification to easily be plugged into a host platform. In addition, the OC-12c ATM adapter subsystem has been designed and developed in order to also be plugged into the same host. The developed architecture has proven very efficient and reliable, providing high-throughput and low-latency bulk data communications. The measured performance on an OC-3c-based (155 Mb/s) testbed has shown that an optimally implemented TCP/IP stack, hosted by a real-time kernel and coupled with an ATM adapter, offers a robust desktop platform for high-speed end-to-end communications. The main feature of the accelerated TCP/IP protocol stack is the out-of-band processing of control and data information. The protocol accelerator embedded system processes the TCP/IP headers and accomplishes checksum computations, while data is transferred from the hosts user memory space directly to the network. Finally, for validation purposes, the prototype system has been incorporated in an existing networking infrastructure targeted to support mass storage applications.

Object oriented prototyping at the system level: an image reconstruction application example

An object oriented (OO) methodology that allows system-level prototyping of embedded applications is presented in this paper. Apart from the typical benefits of OO, i.e. correct capture of specifications, reusability of models and efficient management of design complexity, we also show how an OO system model can be used for guiding the partitioning of the application and for the exploration of alternative implementations. This is demonstrated through a real application from the image processing field.

Integrated microelectronic capacitive readout subsystem for lab-on-a-chip applications

A mixed-signal capacitive biosensor readout system is presented with its main readout functionality embedded in an integrated circuit, compatible with complementary metal oxide semiconductor-type biosensors. The system modularity allows its usage as a consumable since it eventually leads to a system-on-chip where sensor and readout circuitry are hosted on the same die. In this work, a constant current source is used for measuring the input capacitance. Compared to most capacitive biosensor readout circuits, this method offers the convenience of adjusting both the range and the resolution, depending on the requirements dictated by the application. The chip consumes less than 5 mW of power and the die area is 0.06?mm2. It shows a broad input capacitance range (capable of measuring bio-capacitances from 6?pF to 9.8?nF), configurable resolution (down to 1 fF), robustness to various biological experiments and good linearity. The integrated nature of the readout system is proven to be sufficient both for one-time in situ (consumable-type) bio-measurements and its incorporation into a point-of-care system.

A digitally configurable reference capacitance with mismatch compensation for biosensor readout circuits

The most popular capacitance biosensor readout circuits are based on charge sensitive amplifiers. High precision results can be obtained if the difference between the biosensor and a reference capacitance is estimated but this is difficult to be achieved if the range of the biosensor capacitance is wide. In this paper, a novel algorithm implemented in hardware that is used to configure an appropriate reference capacitance close to the biosensor value is presented. The resulting readout circuit is capable of accurately monitoring the changes of a biosensor capacitance, regardless of its initial value. More specifically, the reference capacitance is automatically configured to a value between 0 and 630pF in steps of 10pF. The proposed system can be used to measure an absolute biosensor capacitance of up to 640pF with 2.5fF sensitivity. The 2.5fF resolution is achieved by using a 12-bit ADC instead of a 18-bit ADC that would be required to measure the absolute biosensor capacitance value with the same accuracy. In this way, a lower area/power and higher accuracy readout system can be designed. Of course the capacitance ranges and resolution can be easily adapted to different application requirements.

Analogue current quantizer architectures for implementing integer division-like functions

An analogue current quantization circuit that can implement the integer division by a constant number, the integer floor function, and a function generator with a parametric ladder-like output is presented in this paper. These functions can be exploited in Analogue-to-Digital Converters (ADCs), fuzzy logic and neural networks as well as in signal processing units. Various architecture alternatives are presented which achieve different integer division resolution ranging from 1:2 to 1:65536 or more. High speed and low voltage supply are achieved in ADCs that are based on this divider due to the usage of current mode techniques. Nevertheless, the most important advantages of the presented architectures are the very low power consumption and die area that they require.

Calibration Method for a CMOS 0.06mm^2 150MS/s 8-bit ADC

An ultra low area 8-bit Analog-to-Digital Converter (ADC) has been designed achieving a 150MS/s sampling rate and dissipating 34mW power. It is based on integer division circuits that are arranged in a binary tree structure. We emphasize on the digital calibration method of such an ADC in order to extend its operational temperature range and correct the effect of mismatch and process variations. The calibration is achieved by controlling the voltage supply of the root divider and the amplification and offset correction of the residue that is produced by this divider.

A wireless infrared sensor network for the estimation of the position and orientation of a moving target

The location of a moving person or vehicle in a virtual reality environment is a critical issue. A wireless infrared sensor network capable of estimating the position of a target on a plane and its orientation is presented in this paper. This is actually an extension of the position estimation system that was presented in [1-2] where the target was allowed to move on a plane but not to rotate. In [1-2] the estimation of the position was based on a network consisting of a few low cost infrared transmitters and a pair of infrared receivers mounted on the target. In this paper we discuss how a third infrared sensor properly positioned at the side of the receiver can also allow the estimation of the target orientation.