Alfio Dario Grasso

Advances in Reversed Nested Miller Compensation

The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Design procedures for three-stage CMOS operational transconductance amplifiers employing nested-Miller frequency compensation are presented in this paper. After describing the basic methodology on a Class-A topology, some modifications, to increase swing, slew-rate and current drive capability, are subsequently discussed for a Class-AB solution. The approaches developed are simple as they do not introduce unnecessary circuit constraints and yield accurate results. They are hence suited for a pencil-and-paper design, but can be easily integrated into an analog knowledge-based computer-aided design tool. Experimental prototypes, designed in a 0.35-mum technology by following the proposed procedures, were fabricated and tested. Measurement results were found in close agreement with the target specifications

Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme

A simple compensation strategy, which employs passive components only, is adopted to design a three-stage operational transconductance amplifier (OTA) suitable for driving high capacitive loads. Compared to the classical nested Miller compensation technique, the new solution exploits two additional resistors and allows a reduction in the values of the compensation capacitors of about an order of magnitude. The OTA was fabricated using 0.35-mum CMOS technology and exhibits a 1.4-MHz gain-bandwidth with a load of 500 pF

Analytical comparison of frequency compensation techniques in three‐stage amplifiers

In this paper, design equations of the most common Nested Miller topologies are derived. Moreover, a coherent and comprehensive analytical comparison among the different topologies is also presented. In particular, after deriving design equations, following the approach previously proposed by the authors that have the phase margin as the main design parameter, the different solutions are compared by evaluating a novel figure of merit that expresses a trade-off between gain-bandwidth product, load capacitance and total transconductance, for equal values of phase margin. It is shown that there is no unique optimal solution as this depends on the load condition and the relative magnitude of the transconductance of each stage. From this point of view, the proposed comparison also provides useful design guidelines for the optimization of small-signal performance. Simulations confirming the effectiveness of the comparison are also given. Copyright

Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor

This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances

Two CMOS Current Feedback Operational Amplifiers

Two internally compensated CMOS current-feedback operational amplifiers are discussed in this paper. The circuits are entirely made up of class AB stages, thereby increasing slew rate and drive capability, avoiding many of the drawbacks incurred by previous CMOS and even bipolar implementations. Experimental results on one prototype fabricated in a 0.35-mum process using a 20-pF load and supplied with 3.3 V are also given, showing, as main performance parameters, a SR of 35 V/mus and a constant closed-loop bandwidth (in inverting configuration with a 10-kOmega feedback resistor) of about 2 MHz.

Active reversed nested Miller compensation for three-stage amplifiers

A novel frequency compensation technique for three-stage amplifiers is introduced. Compared to the traditional reversed nested Miller compensation strategy, the proposed one exploits two active stages already included in the amplifier topology, thus no extra circuitry for its implementation is needed. The technique allows to remove the right-half-plane zero and generates a left-half-plane zero, improving the phase margin. Design equations using the phase margin as design parameter are carried out. The proposed technique is used to design, using a standard CMOS 0.35-mum technology, a 2-V three-stage amplifier driving a 500-pF load. The amplifier dissipates 0.24 mW at DC and achieves a 1.75-MHz gain-bandwidth product

Design Methodology of Subthreshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability

A design methodology for three-stage CMOS OTAs operating in the subthreshold region is presented. The procedure is focused on the development of ultra-low-power amplifiers requiring low silicon area but being able to drive high capacitive loads. Indeed, by following the presented methodology we designed a CMOS OTA in a 0.35- μm technology that occupies only 4.4·10-3 mm2, is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF. Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 nW, even under the high load considered. Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than 5 mV/μs with the 200 pF load. Comparison with prior art shows an improvement factor in the figures of merit higher than 5.

Comparison of the Frequency Compensation Techniques for CMOS Two-Stage Miller OTAs

Several design options are nowadays available for the frequency compensation of CMOS two-stage transconductance operational amplifiers, from the traditional Miller approach employing a nulling resistor or a voltage buffer, to a current buffer or the more modern current amplifier. However, designers have no results on the frequency performance achievable that allow to consciously choose the best approach to meet the prescribed specifications efficiently. In this paper, a comparison among the possible Miller approaches is carried out by exploiting an analytical figure of merit that expresses a tradeoff between gain-bandwidth product, load capacitance, and total transconductance for a given value of phase margin. Interesting and useful results, even unexpected, are found. The accuracy of the comparison is also validated through simulations.

Reversed Double Pole-Zero Cancellation Frequency Compensation Technique for Three-Stage Amplifiers

A novel frequency compensation technique for three-stage amplifiers is introduced. The proposed solution exploits two Miller capacitors, two resistors and an additional feedforward stage which can be implemented without entailing extra transistors. Design equations using the phase margin as design parameter are carried out. The technique is used to design, with a standard CMOS 0.35-mum process, a 2-V three-stage amplifier driving a 500-pF load capacitor. The amplifier dissipates only 70muA at DC and achieves a 1.2-MHz gain-bandwidth product, showing a significant improvement in (MHz-pF)/mA performance