Salvatore Pennisi

Advances in Reversed Nested Miller Compensation

The use of two frequency compensation schemes for three-stage operational transconductance amplifiers, namely the reversed nested Miller compensation with nulling resistor (RN-MCNR) and reversed active feedback frequency compensation (RAFFC), is presented in this paper. The techniques are based on the basic RNMC and show an inherent advantage over traditional compensation strategies, especially for heavy capacitive loads. Moreover, they are implemented without entailing extra transistors, thus saving circuit complexity and power consumption. A well-defined design procedure, introducing phase margin as main design parameter, is also developed for each solution. To verify the effectiveness of the techniques, two amplifiers have been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found in good agreement with theoretical analysis and show an improvement in small-signal and large-signal amplifier performances. Finally, an analytical comparison with the nonreversed counterparts topologies, which shows the superiority of the proposed solutions, is also included.

Design methodology and advances in nested-Miller compensation

The nested Miller compensation of three-stage amplifiers is reviewed by using a simple design-oriented approach. The method provides stable amplifiers by accurately controlling the overall phase margin as well as that of the internal loop. Furthermore, the use of nulling resistors to remove the RHP zeros is discussed and optimization criteria are described. A novel technique is presented which allows an amplifiers frequency and settling performance to be greatly improved without increasing power consumption. Thanks to the small compensation capacitors employed, the approach is amenable for integration and in particular where large load capacitors have to be driven. SPICE simulations based on a 0.8-/spl mu/m CMOS design are given and found in remarkable agreement with the theoretical analysis.

Design guidelines for reversed nested Miller compensation in three-stage amplifiers

The reversed nested Miller compensation technique applied to a three-stage operational amplifier is discussed in this paper and new and simple design equations, accurately predicting the loop-gain phase margin, are developed. Techniques for parasitic positive-zero cancellation are also investigated and compared. For this purpose, we found that using nulling resistors is unpractical. Instead, exploiting only one follower (either a voltage or a current one) in the compensation branch results to be more appropriate. Indeed, not only does it avoid any additional constraint on stage transconductance, but it also overcomes the inherent limitations incurred by voltage and current followers when used to compensate two-stage amplifiers. Post-layout simulations on a CMOS opamp using the parameters of a 0.35-/spl mu/m process are found to be in good agreement with the expected results.

Design procedure for two-stage CMOS transconductance operational amplifiers: a tutorial

This paper deals with well-defined designcriteria for two-stage CMOS transconductance operational amplifiers. A novel and simple designprocedure is presented, which allows electricalparameters to be univocally related to the value ofeach circuit element and biasing value. Unlikeprevious methods, the proposed one is suited for apencil-and-paper design and yields accurateperformance optimization without introducingunnecessary circuit constraints. Bandwidthoptimization strategies are also discussed. SPICE simulations based on the proposed procedures aregiven which closely agree the expected results.

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Design procedures for three-stage CMOS operational transconductance amplifiers employing nested-Miller frequency compensation are presented in this paper. After describing the basic methodology on a Class-A topology, some modifications, to increase swing, slew-rate and current drive capability, are subsequently discussed for a Class-AB solution. The approaches developed are simple as they do not introduce unnecessary circuit constraints and yield accurate results. They are hence suited for a pencil-and-paper design, but can be easily integrated into an analog knowledge-based computer-aided design tool. Experimental prototypes, designed in a 0.35-mum technology by following the proposed procedures, were fabricated and tested. Measurement results were found in close agreement with the target specifications

High-frequency harmonic distortion in feedback amplifiers: analysis and applications

An approach for the evaluation of high-frequency harmonic-distortion factors in feedback systems is proposed and the results obtained are applied to feedback amplifiers. Under the assumption that transistors are not driven out of their linear operating regions, small-signal analysis and conventional algebra are exploited to derive understandable and compact expressions highly improving the comprehension of harmonic-distortion generation. The impact of the frequency compensation utilized (namely, dominant-pole or Miller technique) on linearity performance is evaluated and the high-frequency distortion properties of closed-loop single-stage and two-stage amplifiers are analyzed and compared. The accuracy of the analysis, also in view of the given applications, is confirmed through extensive simulations with Spectre on idealized models as well as on CMOS transistor-level circuits. Despite the approximated nature of the analytical models, predicted data are found in very close agreement with simulations in nearly all the frequency range of interest.

Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme

A simple compensation strategy, which employs passive components only, is adopted to design a three-stage operational transconductance amplifier (OTA) suitable for driving high capacitive loads. Compared to the classical nested Miller compensation technique, the new solution exploits two additional resistors and allows a reduction in the values of the compensation capacitors of about an order of magnitude. The OTA was fabricated using 0.35-mum CMOS technology and exhibits a 1.4-MHz gain-bandwidth with a load of 500 pF

Analytical comparison of frequency compensation techniques in three‐stage amplifiers

In this paper, design equations of the most common Nested Miller topologies are derived. Moreover, a coherent and comprehensive analytical comparison among the different topologies is also presented. In particular, after deriving design equations, following the approach previously proposed by the authors that have the phase margin as the main design parameter, the different solutions are compared by evaluating a novel figure of merit that expresses a trade-off between gain-bandwidth product, load capacitance and total transconductance, for equal values of phase margin. It is shown that there is no unique optimal solution as this depends on the load condition and the relative magnitude of the transconductance of each stage. From this point of view, the proposed comparison also provides useful design guidelines for the optimization of small-signal performance. Simulations confirming the effectiveness of the comparison are also given. Copyright

Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor

This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances

High-drive CMOS current amplifier

A high-performance current amplifier is proposed which is based on a folded-cascode transresistance amplifier and a low-distortion class AB current output stage. The loop gain of the transresistance amplifier exhibits a gain bandwidth product of 10 MHz and a DC gain as high as 100 dB which allows accurate closed-loop operations to be achieved. Despite the intrinsic low-linearity performance of current amplifiers with respect to their voltage amplifier counterpart, the proposed circuit provides an output current of 7 mA with a total harmonic distortion (THD) better than -55 dB while requiring only 200 /spl mu/A of quiescent current for the output transistors. The circuit was fabricated in a 1.2 /spl mu/m CMOS process, uses a 5 V power supply, and dissipates 4 mW.