Davide Marano

Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor

This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances

A New Compact Low-Power High-Speed Rail-to-Rail Class-B Buffer for LCD Applications

This paper addresses a very compact low-power class-B buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance, draws a small quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities with a limited power consumption by exploiting two current comparators embodied in the input stage, which sense the input signal transients to turn on the output stage transistors. A rail-to-rail stacked mirror differential amplifier is used to amplify the input signal difference and supply the bias voltages for the output stage. Post-layout simulations show that the proposed buffer can drive a 1-nF column line load within 1.8-¿s settling time under a full voltage swing, while drawing only 3.5-¿A static current from a 3-V power supply. Monte Carlo results finally confirm an excellent degree of robustness of the proposed topology.

Optimized Active Single-Miller Capacitor Compensation With Inner Half-Feedforward Stage for Very High-Load Three-Stage OTAs

This paper introduces a new effective single-Miller capacitor compensation topology for three-stage amplifiers with very large capacitive loads, realized through an active-feedback capacitor together with an inner half-feedforward stage. Moreover, an optimized design strategy which profitably exploits the two left half-plane zeros is presented. To improve the amplifier large signal transient response, the topology also includes an external feedforward path, that only marginally affects the frequency compensation, and a novel slew-rate enhancer section. To validate the solutions presented, a three-stage OTA driving a 10-nF load has been designed and implemented in a standard 0.35-μm CMOS technology. The amplifier occupies less than 0.003-mm2 of die area, provides 2.7-MHz gain-bandwidth product and 0.55-V/μs average slew-rate, while consuming only 25-μA quiescent current.

IMPROVED LOW-POWER HIGH-SPEED BUFFER AMPLIFIER WITH SLEW-RATE ENHANCEMENT FOR LCD APPLICATIONS

The present paper addresses an improved low-power high-speed buffer amplifier topology for large-size liquid crystal display applications. The proposed buffer achieves high-speed driving performance while drawing a low quiescent current during static operation. The circuit offers enhanced slewing capabilities with a limited power consumption by exploiting a slew detector which monitors the output voltage of the input differential amplifier and outputs an additional current signal providing slew-rate enhancement at the output stage. Post-layout simulations show that the proposed buffer can drive a 1 nF column line load with 8.5 V/μs slew-rate and 0.8 μs settling time, while drawing only 8 μA static current from a 3 V power supply.

A new advanced RNMC technique with dual-active current and voltage buffers for low-power high-load three-stage amplifiers

This paper proposes and develops an original power-efficient reversed nested Miller compensation technique for low-power three-stage amplifiers driving large capacitive loads. The proposed approach exploits dual-active buffers in the compensation network, along with a feedforward gain stage providing enhanced speed performance. A well-defined design procedure for the compensation elements is also developed using the loop-gain phase margin as the main design parameter. To confirm the effectiveness of the proposed technique, SPECTRE simulations on a three-stage amplifier driving a 1-nF capacitive load are carried out adopting the model parameters of a standard 0.35µm CMOS technology. Simulation results are finally found to be in excellent agreement with the theoretical analysis, showing a considerable improvement of the proposed strategy over other traditional solutions in terms of small-signal and large-signal performance.

Low-power dual-active class-AB buffer amplifier with self-biasing network for LCD column drivers

This work addresses a new compact low-power highspeed output buffer amplifier topology for large-size LCD applications. The suggested buffer achieves fast driving performance, draws a low quiescent current during static operation and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing capabilities by exploiting the push-pull output sections of two basic complementary-type input amplifiers to realize a dual-path push-pull operation of the output stage. An auxiliary bias network integrated in the input differential stage allows the quiescent conditions of the class-AB output stage to be inherently controlled without additional power dissipation. Post-layout results confirm that the proposed amplifier can drive a 1-nF capacitive load within a 0.9-μs settling time under a 3-V full voltage swing, while drawing only 3.5-μA quiescent current.

Analytical figure of merit evaluation of RNMC networks for low-power three-stage OTAs

In this paper the reversed nested Miller compensation (RNMC) approach is reviewed and its design equations are presented. After introducing two new compensation techniques, a coherent and comprehensive comparison of the available solutions is performed by means of a figure of merit expressing the trade-off among gain-bandwidth product, load capacitance and total transconductance, for equal values of phase margin. The proposed comparison outlines useful design guidelines for the optimization of the overall amplifier performance. Simulations proving the effectiveness of the suggested design methodology and analytical comparison are included, showing the substantial advantage of one of the proposed solutions.

Step-response optimization techniques for low-power three-stage operational amplifiers for large capacitive load applications

This paper proposes and develops two simple efficient techniques for optimizing the closed-loop transient response of three-stage amplifiers for large capacitive load applications. The proposed approaches exploit a current comparator in the inner amplifier nodes to sense the input voltage transients and switch on an auxiliary driving device providing slew-rate enhancement and settling time improvement without extra static power dissipation. SPECTRE simulations are carried out on a three-stage amplifier adopting a recently proposed RNMC strategy with a voltage follower and two resistors. Simulation results confirm the effectiveness of both proposed techniques, showing a symmetrical step-response with a significant improvement in large-signal speed performance. Both discussed solutions are suitable for any particular three-stage amplifier topology and are also independent of the adopted compensation network.

An efficient RNM compensation topology with voltage buffer and nulling resistors for large-capacitive-load three-stage OTAs

This work proposes and develops an original compensation approach for low-power three-stage operational transconductance amplifiers driving large capacitive loads. The proposed solution is based on the basic reversed nested Miller compensation and exploits a voltage buffer and two nulling resistors in the compensation network, along with a feedforward stage to improve slewing and settling performance. A well-defined design procedure using the loop gain phase margin as the main design parameter is also developed. Simulations on a three-stage amplifier are carried out and are found to be in excellent agreement with the theoretical analysis, showing a significant improvement of the proposed approach over traditional compensation strategies in terms of small-signal and large-signal performance.

Self-biased dual-path push-pull output buffer amplifier topology for LCD driver applications

The present paper addresses an improved and compact low-power high-speed buffer amplifier topology for large-size liquid crystal display drivers. The proposed buffer achieves fast driving performance, draws a low quiescent current and offers a rail-to-rail common-mode input range. The circuit provides enhanced slewing and settling capabilities by realizing a dual-path push-pull operation of the output stage. No additional bias network is required to fix the quiescent conditions of the class-AB output stage, since the output static current is inherently controlled by the input differential stage itself without auxiliary power dissipation. Simulation results demonstrate that the suggested buffer can drive a 1000-pF column line capacitive load with a 5.8-V/µs slew-rate and a 0.75-µs settling time, while drawing only 3-µA quiescent current from a 3-V power supply.