Alfonso Sánchez-Macián

Hamming SEC-DAED and Extended Hamming SEC-DED-TAED Codes Through Selective Shortening and Bit Placement

Radiation particles can impact registers or memories creating soft errors. These errors can modify more than one bit causing a multiple cell upset (MCU) which consists of errors in registers or memory cells that are physically close. These MCUs can affect a single word, producing adjacent bit errors. Hamming codes are commonly used to protect memories or registers from soft errors. However, when multiple errors occur, a Hamming code may not detect them. In this letter, single-error-correction double adjacent error detection Hamming codes are presented for 16-, 32-, and 64-bit words. Additionally, single-error-correction double-error-detection triple adjacent error detection codes based on extended Hamming are presented as well. The enhanced detection is achieved by performing a selective shortening and reordering of the Hamming matrix so adjacent errors result in a syndrome that does not match that of any single error. These codes will help in the detection of MCUs in SRAM memory designs.

Enhanced Detection of Double and Triple Adjacent Errors in Hamming Codes Through Selective Bit Placement

Hamming codes that can correct one error per word are widely used to protect memories or registers from soft errors. As technology scales, radiation particles that create soft errors are more likely to affect more than 1 b when they impact a memory or electronic circuit. This effect is known as a multiple cell upset (MCU), and the registers or memory cells affected by an MCU are physically close. To avoid an MCU from causing more than one error in a given word, interleaving is commonly used in memories. With interleaving, cells that belong to the same logical word are placed apart such that an MCU affects multiple bits but on different words. However, interleaving increases the complexity of the memory device and is not suitable for small memories or content-addressable memories. When interleaving is not used, MCUs can cause multiple errors in a word that may not even be detected by a Hamming code. In this paper, a technique to increase the probability of detecting double and triple adjacent errors when Hamming codes are used is presented. The enhanced detection is achieved by placing the bits of the word such that adjacent errors result in a syndrome that does not match that of any single error. Double and triple adjacent errors are precisely the types of errors that an MCU would likely cause, and therefore, the proposed scheme will be useful to provide error detection for MCUs in memory designs.

An energy consumption model for Energy Efficient Ethernet switches

Ethernet is one of the first computer networking technologies for which a standard has been developed to improve its energy efficiency. The Energy Efficient Ethernet (IEEE 802.3az) standard was approved in 2010 and is expected to enable savings of several Terawatt hours (TWh) per year. As switches that implement the standard become available and are deployed, it is important to understand how their energy consumption depends on the number of active ports and their traffic. In this paper the energy consumption of small Energy Efficient Ethernet switches is analyzed in several experiments and based on the results a model for the energy consumption of Energy Efficient Ethernet switches is proposed. The model can be used to predict the energy savings when deploying the new switches and also for research on further energy saving techniques such as energy efficient routing or dynamic link shutdown.

Using coordinated transmission with energy efficient ethernet

IEEE 802.3az Energy Efficient Ethernet (EEE) supports link active and sleep (idle) modes as a means of reducing the energy consumption of lightly utilized Ethernet links. A link wakes-up when an interface has packets to send and returns to idle when there are no packets. In this paper, we show how Coordinated Transmission (CT) in a 10GBASE-T link can allow for key physical layer (PHY) components to be shutdown to further reduce Ethernet energy consumption and enable longer cable lengths. CT is estimated to enable an additional 25% energy savings with a trade-off of an added frame latency of up to 40 µs, which is expected to have a negligible impact on most applications. The effective link capacity is approximately 4 Gb/s for symmetric traffic and close to 7 Gb/s for asymmetric traffic. This can be sufficient in many situations. Additionally a mechanism to switch to the normal full-duplex mode is proposed to allow for full link capacity when needed while retaining the additional energy savings when the link load is low.

A Method to Extend Orthogonal Latin Square Codes

Error correction codes (ECCs) are commonly used to protect memories from errors. As multibit errors become more frequent, single error correction codes are not enough and more advanced ECCs are needed. The use of advanced ECCs in memories is, however, limited by their decoding complexity. In this context, one-step majority logic decodable (OS-MLD) codes are an interesting option as the decoding is simple and can be implemented with low delay. Orthogonal Latin squares (OLS) codes are OS-MLD and have been recently considered to protect caches and memories. The main advantage of OLS codes is that they provide a wide range of choices for the block size and the error correction capabilities. In this brief, a method to extend OLS codes is presented. The proposed method enables the extension of the data block size that can be protected with a given number of parity bits thus reducing the overhead. The extended codes are also OS-MLD and have a similar decoding complexity to that of the original OLS codes. The proposed codes have been implemented to evaluate the circuit area and delay needed for different block sizes.

Combined SEU and SEFI Protection for Memories Using Orthogonal Latin Square Codes

Radiation effects cause several types of errors on memories including single event upsets (SEUs) or single event functional interrupts (SEFIs). Error correction codes (ECCs) are widely used to protect against those errors. For a number of reasons, there is a large interest in using double data rate type three (DDR-3) synchronous dynamic random-access (SDRAM) memories in space applications. Radiation testing results show that these memories will suffer both SEUs and SEFIs when used in space. Protection against a SEFI and an SEU is needed to achieve high reliability. In this paper, a method to protect 16-bit and 64-bit data word memories composed of 8-bit memory devices against a simultaneous SEFI and an SEU is presented. The scheme uses orthogonal Latin square (OLS) codes and can be activated when a SEFI occurs, using a conventional double error correction approach otherwise.

Low Power embedded DRAM caches using BCH code partitioning

Technology advances have recently enabled the use of DRAMs into logic integrated circuits. These embedded DRAMs can be used to efficiently implement caches since DRAMs require substantially less area than SRAMs. One challenge for DRAM based caches is that a small time between refreshes is needed to ensure data retention. These refreshes increase the power consumption even when the cache is idle. To mitigate this issue, the use of longer times between refreshes combined with the use of Error Correction Codes (ECCs) has been recently proposed. The idea is that the time between refreshes can be increased significantly while only causing data retention failures on a small percentage of the cells. Then those errors can be corrected by the ECC. For this scheme to be efficient the number of additional bits required by the ECC should be small. This is achieved by using large data blocks for the ECC which in turns means that a large data block has to be accessed even when only a small portion of it is needed. This has no effect on idle power consumption but increases the dynamic power consumption and reduces the effective memory bandwidth. In this paper, a technique to mitigate this issue is proposed. It enables better granularity in the read data accesses by partitioning the ECC block into two sub-blocks and modifying the error detection and correction processes. This reduces the dynamic power consumption and increases the available memory bandwidth while requiring only a moderate increase in the number of additional bits.

On the impact of the TCP acknowledgement frequency on energy efficient ethernet performance

With the adoption of the recently approved Energy Efficient Ethernet standard, frame scheduling will have a significant impact on Energy Consumption. Acknowledgements are large percentage of frames in Transmission Control Protocol sessions. In this paper the impact of different TCP acknowledgement policies on the energy consumption of Ethernet Networks is analyzed.

An experimental power profile of Energy Efficient Ethernet switches

The access network is believed to account for 70-80% of the overall energy consumption of wired networks, attributable in part to the large number of small and inefficient switches deployed in typical homes and enterprises. In order to reduce the per-bit energy consumption of such devices, the Energy Efficient Ethernet (EEE) standard was approved as IEEE 802.3az in 2010 with the aim of making Ethernet devices more energy efficient. However, the potential for energy savings, and their dependence on traffic characteristics, is poorly understood. This paper undertakes a comprehensive study of the energy efficiency of EEE, and makes three new contributions: first, we perform extensive measurements on three commercial EEE switches, and show how their power consumption profile depends on factors such as port counts, traffic loads, packet sizes, and traffic burstiness. Second, we develop a simple yet powerful model that gives analytical estimates of the power consumption of EEE switches under various traffic conditions. Third, we validate the energy savings via experiments in typical deployment scenarios, and estimate the overall reduction in annual energy costs that can be realized with widespread adoption of EEE in the Internet.

A Scheme to Reduce the Number of Parity Check Bits in Orthogonal Latin Square Codes

The use of error-correcting codes is a common strategy to protect memories from errors. Single-error correction, double-error detection linear block codes have been traditionally utilized. However, there are applications where multiple errors are frequent and more complex codes are needed. Orthogonal Latin square codes are one type of codes with multiple-error-correction capability. They are of interest for memory protection because they can be decoded with low complexity and delay. This paper presents a modification to orthogonal Latin square codes that reduces the number of parity check bits to be stored in memory therefore lowering the memory overhead needed to implement the codes. The proposed codes can also be decoded with low delay and complexity. This paper also presents an evaluation of the encoder and decoder implementations for various word sizes and compares them with the standard orthogonal Latin square implementations. The results show that they are similar in terms of circuit area and introduce only a small penalty in delay.