Alfredo Rosado

An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links

Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance.

Instrumentation, control, and automation for submerged anaerobic membrane bioreactors.

A submerged anaerobic membrane bioreactor (AnMBR) demonstration plant with two commercial hollow-fibre ultrafiltration systems (PURON®, Koch Membrane Systems, PUR-PSH31) was designed and operated for urban wastewater treatment. An instrumentation, control, and automation (ICA) system was designed and implemented for proper process performance. Several single-input-single-output (SISO) feedback control loops based on conventional on–off and PID algorithms were implemented to control the following operating variables: flow-rates (influent, permeate, sludge recycling and wasting, and recycled biogas through both reactor and membrane tanks), sludge wasting volume, temperature, transmembrane pressure, and gas sparging. The proposed ICA for AnMBRs for urban wastewater treatment enables the optimization of this new technology to be achieved with a high level of process robustness towards disturbances.

Application of ARMA modeling to the improvement of weight estimations in fruit sorting and grading machinery

Accurate weighting of pieces in different sorts of conveyor belts or articulated chains at fast speed is a key feature in many industrial processes. This paper presents a procedure to improve the performance, whether increasing speed or accuracy, of the load-cell-based weighting subsystem in a fruit sorting and grading machine to achieve an accuracy of /spl plusmn/1 gram at a speed of 20 fruits per seconds. The proposed solution includes a signal preprocessing based on a previous ARMA modeling of the weighting subsystem response plus a power line-noise removal and a simple sample averaging in the plateau. The procedure has been tested off-line using real signals acquired from a prototype machine.

Fast spiking neural network architecture for low-cost FPGA devices

Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a postsynaptic output spike generation. In order to model a real biological system by artificial SNN, the number of required neurons is very high (thousands). In this work, we propose a SNN architecture able to adapt big size networks using reduced hardware resources. While spikes are processed at 1ms time, inter spike time is used for internal calculations, a mixed serial-parallel structure allows optimized computation of all neuron output values. Results show that SNN can be accommodated using a medium-size FPGA device such as Xilinx Spartan 3 with processing speed comparable to fully parallel implementations with up to 70% resource reduction.

Hardware-efficient matrix inversion algorithm for complex adaptive systems

This work shows an FPGA implementation for the matrix inversion algebra operation. Usually, large matrix dimension is required for real-time signal processing applications, especially in case of complex adaptive systems. A hardware efficient matrix inversion procedure is described using QR decomposition of the original matrix and modified Gram-Schmidt method. This works attempts a direct VHDL description using few predefined packages and fixed point arithmetic for better optimization. New proposals for intermediate calculations are described, leading to efficient logic occupation together with better performance and accuracy in the vector space algebra. Results show that, for a relatively small device as Xilinx Spartan3 XC3S1000, a matrix size up to 23 × 23 can be implemented, having a matrix inversion computation time of 253μs. Accuracy results compared to floating point computation and an estimation of required clock cycles as a function of matrix size are analyzed.

High performance hardware correlation coefficient assessment using programmable logic for ECG signals

Abstract Correlation coefficient is frequently used to obtain cardiac rhythm by peak estimation and appreciate differences in the signal compared to a pattern. This work focuses on the description of a real-time correlation assessment procedure. Applied to electrocardiogram (ECG) signals, a new correlation value is obtained every new sample and pulse detection information is provided. The ECG pattern is internally stored and can be changed when desired. This procedure is useful in Systems on Chip implementation and can be applied to design compact ECG monitoring systems consisting on a system on chip where programmable logic offloads the main processor. A Xilinx FPGA device has been used for prototyping.

Fast non-invasive ventricular fibrillation detection method using pseudo Wigner-Ville distribution

Detection of ventricular fibrillation (VF) at an early stage is crucial in order to lower the risk of sudden death and allow the specialist to have a greater reaction time to give the patient a good recovering therapy and avoid unrecoverable damage to the cardiac tissue. We present an algorithm oriented towards the real-time detection of VF, to be used as a part of monitoring systems in intensive care units or ambulatory centres. The study has been done using the AHA (American Heart Association) database, focusing mainly on the 8200 series, and the MIT (Massachussetts Institute of Technology) database. The detection algorithm combines both time-domain and time-frequency parameters. Using the appropriate parameters, the detection algorithm discerns between VF and non-VF rhythms, including VF-like rhythms like certain types of ventricular tachycardia (VT). A VF flutter sensitivity of 86% and an average specificity of 94.3 % (including VT separation) is obtained.

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

Address-Event-Representation (AER) is a widely extended asynchronous technique for interchanging “neural spikes” among different hardware elements in Neuromorphic Systems. Conventional AER links use parallel physical wires together with a pair of handshaking signals (Request and Acknowledge). Here we present a fully serial implementation using bidirectional SATA connectors with a pair of LVDS (low voltage differential signaling) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links per LVDS physical connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs reaching a maximum event transmission speed of 75Meps (Mega Events per second) for 32-bit events at 3.0Gbps line data rate.

Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise

Adaptive filters are used in a wide range of applications such as noise cancellation, system identification, and prediction. One of the main problems for theses filters is the impulsive noise as it generates algorithm unstability. This work shows the development, simulation and hardware implementation of a new algorithm robust to impulsive noise. Hardware implementation becomes essential in many cases where a real time execution, reduced size, or low power system is needed. An efficient hardware architecture is proposed and different optimizations for size and speed are developed: no need for control state machine, reduced computation requirements due to simplifications, etc. Furthermore, two different implementations were done to test two simplified cost functions. Finally, comparison results are provided to test accuracy, performance and logic occupation, showing an efficient architecture for impulsive noise robustness.

Analysis of heart rate variability in diabetic patients affected by autonomic cardiovascular neuropathy

In this paper, time- and frequency-domain parameters of the heart rate variability (HRV) are investigated in 45 Holter records for a group of diabetic patients with neuropathy (DNG) other group of diabetics without neuropathy (DWNG) and the control group (CG). Obtained results show that: 1) DNG vs. CG present significant differences of parameters in time- and frequency-domain at diurnal and nocturnal periods. 2) Only frequency-domain parameters can distinguish diabetic patients with and without neuropathy. 3) No differences have been appreciated between control and diabetic patients without neuropathy.