Taras Iakymchuk

An AER handshake-less modular infrastructure PCB with x8 2.5Gbps LVDS serial links

Nowadays spike-based brain processing emulation is taking off. Several EU and others worldwide projects are demonstrating this, like SpiNNaker, BrainScaleS, FACETS, or NeuroGrid. The larger the brain process emulation on silicon is, the higher the communication performance of the hosting platforms has to be. Many times the bottleneck of these system implementations is not on the performance inside a chip or a board, but in the communication between boards. This paper describes a novel modular Address-Event-Representation (AER) FPGA-based (Spartan6) infrastructure PCB (the AER-Node board) with 2.5Gbps LVDS high speed serial links over SATA cables that offers a peak performance of 32-bit 62.5Meps (Mega events per second) on board-to-board communications. The board allows back compatibility with parallel AER devices supporting up to x2 28-bit parallel data with asynchronous handshake. These boards also allow modular expansion functionality through several daughter boards. The paper is focused on describing in detail the LVDS serial interface and presenting its performance.

Fast spiking neural network architecture for low-cost FPGA devices

Spiking Neural Networks (SNN) consist of fully interconnected computation units (neurons) based on spike processing. This type of networks resembles those found in biological systems studied by neuroscientists. This paper shows a hardware implementation for SNN. First, SNN require the inputs to be spikes, being necessary a conversion system (encoding) from digital values into spikes. For travelling spikes, each neuron interconnection is characterized by weights and delays, requiring an internal neuron processing by a Postsynaptic Potential (PSP) function and membrane potential threshold evaluation for a postsynaptic output spike generation. In order to model a real biological system by artificial SNN, the number of required neurons is very high (thousands). In this work, we propose a SNN architecture able to adapt big size networks using reduced hardware resources. While spikes are processed at 1ms time, inter spike time is used for internal calculations, a mixed serial-parallel structure allows optimized computation of all neuron output values. Results show that SNN can be accommodated using a medium-size FPGA device such as Xilinx Spartan 3 with processing speed comparable to fully parallel implementations with up to 70% resource reduction.

Hardware-efficient matrix inversion algorithm for complex adaptive systems

This work shows an FPGA implementation for the matrix inversion algebra operation. Usually, large matrix dimension is required for real-time signal processing applications, especially in case of complex adaptive systems. A hardware efficient matrix inversion procedure is described using QR decomposition of the original matrix and modified Gram-Schmidt method. This works attempts a direct VHDL description using few predefined packages and fixed point arithmetic for better optimization. New proposals for intermediate calculations are described, leading to efficient logic occupation together with better performance and accuracy in the vector space algebra. Results show that, for a relatively small device as Xilinx Spartan3 XC3S1000, a matrix size up to 23 × 23 can be implemented, having a matrix inversion computation time of 253μs. Accuracy results compared to floating point computation and an estimation of required clock cycles as a function of matrix size are analyzed.

Hardware-accelerated spike train generation for neuromorphic image and video processing

Recent studies concerning Spiking Neural Networks show that they are a powerful tool for multiple applications as pattern recognition, image tracking, and detection tasks. The basic functional properties of SNN reside in the use of spike information encoding as the neurons are specifically designed and trained using spike trains. We present a novel and efficient frequency encoding algorithm with Gabor-like receptive fields using probabilistic methods and targeted to FPGA for online pro-cessing. The proposed encoding is versatile, modular and, when applied to images, it is able to perform simple image transforms as edge detection, spot detection or removal, and Gabor-like filtering without any further computation requirements. The algorithm is implemented in FPGA and ready to be used in embedded systems, being capable of processing images or video stream up to 40 megapixel per second per single core. Results show an improvement in hardware occupation and encoding speed up to 2.5x over existing state of the art implementations.

Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

Address-Event-Representation (AER) is a widely extended asynchronous technique for interchanging “neural spikes” among different hardware elements in Neuromorphic Systems. Conventional AER links use parallel physical wires together with a pair of handshaking signals (Request and Acknowledge). Here we present a fully serial implementation using bidirectional SATA connectors with a pair of LVDS (low voltage differential signaling) wires for each direction. The proposed implementation can multiplex a number of conventional parallel AER links per LVDS physical connection. It uses flow control, clock correction, and byte alignment techniques to transmit 32-bit address events reliably over multiplexed serial connections. The setup has been tested using commercial Spartan6 FPGAs reaching a maximum event transmission speed of 75Meps (Mega Events per second) for 32-bit events at 3.0Gbps line data rate.

Frequency spike encoding using Gabor-like receptive fields

Abstract Spiking Neural Networks (SNN) are a popular field of study. For a proper development of SNN algorithms and applications, special encoding methods are required. Signal encoding is the first step since signals need to be converted into spike trains as the primary input to an SNN. We present an efficient frequency encoding system using receptive fields. The proposed encoding is versatile and it can provide simple image transforms like edge detection, spot detection or removal, or Gabor-like filtering. The proposed encoding can be used in many application areas as image processing and signal processing for detection and classification.

Implementation of a new adaptive algorithm using fuzzy cost function and robust to impulsive noise

Adaptive filters are used in a wide range of applications such as noise cancellation, system identification, and prediction. One of the main problems for theses filters is the impulsive noise as it generates algorithm unstability. This work shows the development, simulation and hardware implementation of a new algorithm robust to impulsive noise. Hardware implementation becomes essential in many cases where a real time execution, reduced size, or low power system is needed. An efficient hardware architecture is proposed and different optimizations for size and speed are developed: no need for control state machine, reduced computation requirements due to simplifications, etc. Furthermore, two different implementations were done to test two simplified cost functions. Finally, comparison results are provided to test accuracy, performance and logic occupation, showing an efficient architecture for impulsive noise robustness.

Live demonstration: Multiplexing AER asynchronous channels over LVDS links with flow-control and clock-correction for scalable neuromorphic systems

In this live demonstration we exploit the use of a serial link for fast asynchronous communication in massively parallel processing platforms connected to a DVS for real-time implementation of bio-inspired vision processing on spiking neural networks.

Event-based encoding from digital magnetic compass and ultrasonic distance sensor for navigation in mobile systems

Event-based encoding reduces the amount of generated data while keeping relevant information in the measured magnitude. While this encoding is mostly associated with spiking neuromorphic systems, it can be used in a broad spectrum of tasks. The extension of event-based data representation to other sensors would provide advantages related to bandwidth reduction, lower computing requirements, increased processing speed and data processing. This work describes two event-based encoding procedures (magnitude-event and rate-event) for two sensors widely used in industry, especially for navigation in mobile systems: digital magnetic compass and ultrasonic distance sensor. Encoded data meet Address Event Representation (AER) format for further transmission, processing and visualization. Two encoding procedures and their associated AER conversion from sensor data are described, using an AVR microprocontroller to perform the task in real-time. Results are transmitted to a computer via USART, displayed and recorded using Matlab or jAER visualization tool. A comparison with classic transmitting and processing of sensor data is done to evaluate the convenience of the proposed encoding. Results show that data transmission bandwith can be reduced up to 95% under certain conditions, envisaging that pure or mixed regular/event-based data sensors are desirable for high speed transmission and low computer processing while keeping relevant information, which is highly desirable for mobile systems.

Novel Resistance Measurement Method: Analysis of Accuracy and Thermal Dependence with Applications in Fiber Materials

Material resistance is important since different physicochemical properties can be extracted from it. This work describes a novel resistance measurement method valid for a wide range of resistance values up to 100 GΩ at a low powered, small sized, digitally controlled and wireless communicated device. The analog and digital circuits of the design are described, analysing the main error sources affecting the accuracy. Accuracy and extended uncertainty are obtained for a pattern decade box, showing a maximum of 1% accuracy for temperatures below 30 ∘C in the range from 1 MΩ to 100 GΩ. Thermal analysis showed stability up to 50 ∘C for values below 10 GΩ and systematic deviations for higher values. Power supply Vi applied to the measurement probes is also analysed, showing no differences in case of the pattern decade box, except for resistance values above 10 GΩ and temperatures above 35 ∘C. To evaluate the circuit behaviour under fiber materials, an 11-day drying process in timber from four species (Oregon pine-Pseudotsuga menziesii, cedar-Cedrus atlantica, ash-Fraxinus excelsior, chestnut-Castanea sativa) was monitored. Results show that the circuit, as expected, provides different resistance values (they need individual conversion curves) for different species and the same ambient conditions. Additionally, it was found that, contrary to the decade box analysis, Vi affects the resistance value due to material properties. In summary, the proposed circuit is able to accurately measure material resistance that can be further related to material properties.