Ali Afsahi

A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier

The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power management units can be easily shared. This paper presents a solution in which 802.11a/b/g WLAN, single-stream 11n (SSN) WLAN, BT, and FM subsystem and radio are integrated on a single die.

Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2

Fully integrated dual-band power amplifiers with on-chip baluns for 802.11n MIMO WLAN applications are presented. With a 3.3 V supply, the PAs produce a saturated output power of 28.3 dBm and 26.7 dBm with peak drain efficiency of 35.3% and 25.3% for the 2.4 GHz and 5 GHz bands, respectively. By utilizing multiple fully self-contained linearization algorithms, an EVM of -25 dB is achieved at 22.4 dBm for the 2.4 GHz band and 20.5 dBm for the 5 GHz band while transmitting 54 Mbs OFDM. The chip is fabricated in standard 65 nm CMOS and the PAs occupy 0.31 mm2 (2.4 GHz) and 0.27 mm2 (5 GHz) area. To examine the reliability of the PAs, accelerated aging tests are performed for several hundreds parts without a single failure.

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The integration of the power amplifier (PA) is one of the greatest challenges facing the designers of complex wireless SoCs. Recently, there has been a significant effort to implement PAs in CMOS [1–4]. The 802.11g standard utilizes OFDM modulation, which has a very high peak-to-average ratio (PAR) and therefore requires a highly linear PA. In addition, WLAN SoCs are evolving to accommodate more advanced applications, like the transmission and reception of multiple streams of high-definition video across long distances. This requires a higher linear transmit power. However, the low power supply, lossy substrate and lower breakdown voltage make the design of a linear, high power, high efficiency and reliable CMOS PA quite challenging. In this paper, a linear 65nm CMOS PA operating at 3.3V supply with an on-chip distributed LC power combining network and improved linearization is presented. The result is the highest combination of output power and efficiency yet reported for a packaged linear WLAN amplifier at 2.4GHz in a CMOS process.

2 802.11n MIMO WLAN SoC

Fully integrated dual-band power amplifiers with on-chip baluns for 802.11n MIMO WLAN applications are presented. With a 3.3v supply, the PAs produce a saturated output power of 28.3dBm and 26.7dBm with peak drain efficiency of 35.3% and 25.3% for the 2.4GHz and 5GHz bands, respectively. By utilizing multiple fully self-contained linearization algorithms, an EVM of −25dB is achieved at 22.4dBm for the 2.4GHz band and 20.5dBm for the 5GHz band while transmitting 54Mbs OFDM. The chip is fabricated in standard 65nm CMOS and the PAs occupy 0.31mm2 (2.4G) and 0.27mm2 (5G) area.

A 65nm CMOS 2.4GHz 31.5dBm power amplifier with a distributed LC power-combining network and improved linearization for WLAN applications

Two monolithic power combining schemes for CMOS power amplifiers (PAs)-distributed LC and current-mode transformer-based-are compared. Fully integrated 2.4-GHz PAs using these techniques were fabricated in a 65-nm standard CMOS technology. From a 3.3-V supply, the distributed-LC combined PA produces a saturated power of 31.5 dBm with peak power-added efficiency (PAE) of 25%. The current-mode transformer-based PA combiner produces 33.5-dBm saturated power with 37.6% peak PAE. With gm -linearization and digital pre-distortion, these PAs transmit 25.5 and 26.4 dBm with - 25-dB error vector magnitude for a 54-Mb/s orthogonal frequency division multiplexing signal, respectively.

Fully integrated dual-band power amplifiers with on-chip baluns in 65nm CMOS for an 802.11n MIMO WLAN SoC

A low-power 802.11abg SoC which achieves the best reported sensitivity as well as lowest reported power consumption and utilizes an extensive array of auto calibrations is reported. This SoC utilizes a two-antenna array receiver to build a single weight combiner (SWC) system. A new signal-path Cartesian phase generation and combination technique is proposed that shifts the RF signal in 22.5deg phase steps. A 3 dB improvement in received SNR is achieved in comparison to the single path receiver. The radio and AFE occupy 10 mm2 of area in a digital 0.13 mum CMOS process of which 0.29 mm2 is occupied by the SWC RF receiver. The radio+AFE consume 85 mW of power in active Rx mode of which 30 mW is utilized by the SWC RF front-end.

Monolithic Power-Combining Techniques for Watt-Level 2.4-GHz CMOS Power Amplifiers for WLAN Applications

An integrated linear 2.4GHz CMOS power amplifier is presented. With a 3.3v supply, the PA produces a saturated output power of 33.5dBm with peak drain and power-added efficiencies of 44.2% and 37.6%, respectively and has 40dB small-signal gain. By utilizing gm-linearization and digital pre-distortion, an EVM of −25dB is achieved at 26.4dBm with 22% PAE while transmitting 54Mbs OFDM. The chip is fabricated in standard 65nm CMOS and packaged in a 40-pin QFN package. The PA occupies 2.2mm2 active area.

A Low-Power Single-Weight-Combiner 802.11abg SoC in 0.13 µm CMOS for Embedded Applications Utilizing An Area and Power Efficient Cartesian Phase Shifter and Mixer Circuit

A two-antenna array receiver is designed for WLAN application to build a maximum ratio combiner (MRC) system. A new signal-path Cartesian phase generation and combination technique is proposed to shift the RF signal by 22.5 phase steps. The 3 dB improvement in received SNR is achieved in comparison to single path receiver. The 0.29 mm^2 RF paths consumes 30 mW in 0.13 mum CMOS process.

An integrated 33.5dBm linear 2.4GHz power amplifier in 65nm CMOS for WLAN applications

A 2.4GHz fully integrated power amplifier with an on-chip balun for embedded WLAN applications with direct battery connection (2.3–5.5V) is presented. With a switched programmable feedback bias network, the PA can deliver 23.5dBm to 28.4dBm CW saturated power and 18.2dBm to 23.2dBm OFDM linear power (−25dB EVM) with PAPD when the supply varies from 2.3V to 5.5V. The PA occupies 1.2mm2 in 65nm CMOS.

An Area and Power Efficient Cartesian Phase Shifter + Mixer Circuit Applied to WLAN System

Envelope tracking (ET) has become popular for enhancing battery life in mobile communication devices that employ high peak-to-average power ratio (PAPR) signals. Most of the published ET systems have focused either on narrow-bandwidth standards, 20MHz WLAN, or LTE [1–3]. However, as the demand for higher bandwidths and data-rates increases, so does the need for wideband ET solutions. Furthermore, to support modulations with different PAPR and transmit powers, the PA will likely require seamless switching between a continuous ET mode and a fixed-supply mode (as with a low drop-out regulator, i.e. a LDO). Hence, fast reconfigurability is needed, which most published ET systems lack. This paper describes a fully integrated, reconfigurable WLAN ET system with digital baseband in a 28nm CMOS technology for bandwidths up to 40MHz. The ET modulator directly interfaces with a battery (Vbat) and is fully integrated within a complete WLAN transceiver with RF, digital, and frequency synthesizer circuitry.