Arya Reza Behzad

A Fully Integrated MIMO Multi-Band Direct-Conversion CMOS Transceiver for WLAN Applications (802.11n)

A single-chip multi-band direct-conversion CMOS MIMO transceiver (2 times 2) targeted for WLAN applications is presented. This transceiver is capable of satisfying the requirements of the Enhanced Wireless Consortium and achieves PHY rates of >270Mb/s. The receivers and transmitters achieve an EVM of better than -41 dB (0.9%) and -40dB (1.0%) operating in legacy g and a modes, respectively. From a 1.8V supply and with both cores operating, the chip draws 275mA in RX mode and 280mA in TX mode.

A 5-GHz direct-conversion CMOS transceiver utilizing automatic frequency control for the IEEE 802.11a wireless LAN standard

A fully integrated CMOS direct-conversion 5-GHz transceiver with automatic frequency control is implemented in a 0.18-/spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution The transceiver consumes 150 mW in receive mode and 380 mW in transmit mode while transmitting +15-dBm output power. The receiver achieves a sensitivity of better than -93.7dBm and -73.9dBm for 6 Mb/s and 54 Mb/s, respectively (even using hard-decision decoding). The transceiver achieves a 4-dB receive noise figure and a +23-dBm transmitter saturated output power. The transmitter also achieves a transmit error vector magnitude of -33 dB. The IC occupies a total die area of 11.7 mm/sup 2/ and is packaged in a 48-pin LPCC package. The chip passes better than /spl plusmn/2.5-kV ESD performance. Various integrated self-contained or system-level calibration capabilities allow for high performance and high yield.

A multistandard, multiband SoC with integrated BT, FM, WLAN radios and integrated power amplifier

The growing occurrences of WLAN, BT, and FM on the same mobile device have created a demand for putting all three on the same die to save on die size, I/O count, BOM, and ultimately cost. Common blocks such as crystal oscillator, bandgap, and power management units can be easily shared. This paper presents a solution in which 802.11a/b/g WLAN, single-stream 11n (SSN) WLAN, BT, and FM subsystem and radio are integrated on a single die.

Direct-conversion CMOS transceiver with automatic frequency control for 802.11a wireless LANs

A 11.7mm/sup 2/ 5GHz direct-conversion 0.18/spl mu/m CMOS transceiver achieves a sensitivity of -93dBm, a system NF of 4.5dB (high gain), and IIP3 of -4.8dBm (low gain). Dissipation is 150mW in RX mode and 380mW while transmitting 15dBm OFDM signal.

Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2

Fully integrated dual-band power amplifiers with on-chip baluns for 802.11n MIMO WLAN applications are presented. With a 3.3 V supply, the PAs produce a saturated output power of 28.3 dBm and 26.7 dBm with peak drain efficiency of 35.3% and 25.3% for the 2.4 GHz and 5 GHz bands, respectively. By utilizing multiple fully self-contained linearization algorithms, an EVM of -25 dB is achieved at 22.4 dBm for the 2.4 GHz band and 20.5 dBm for the 5 GHz band while transmitting 54 Mbs OFDM. The chip is fabricated in standard 65 nm CMOS and the PAs occupy 0.31 mm2 (2.4 GHz) and 0.27 mm2 (5 GHz) area. To examine the reliability of the PAs, accelerated aging tests are performed for several hundreds parts without a single failure.

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The integration of the power amplifier (PA) is one of the greatest challenges facing the designers of complex wireless SoCs. Recently, there has been a significant effort to implement PAs in CMOS [1–4]. The 802.11g standard utilizes OFDM modulation, which has a very high peak-to-average ratio (PAR) and therefore requires a highly linear PA. In addition, WLAN SoCs are evolving to accommodate more advanced applications, like the transmission and reception of multiple streams of high-definition video across long distances. This requires a higher linear transmit power. However, the low power supply, lossy substrate and lower breakdown voltage make the design of a linear, high power, high efficiency and reliable CMOS PA quite challenging. In this paper, a linear 65nm CMOS PA operating at 3.3V supply with an on-chip distributed LC power combining network and improved linearization is presented. The result is the highest combination of output power and efficiency yet reported for a packaged linear WLAN amplifier at 2.4GHz in a CMOS process.

2 802.11n MIMO WLAN SoC

Fully integrated dual-band power amplifiers with on-chip baluns for 802.11n MIMO WLAN applications are presented. With a 3.3v supply, the PAs produce a saturated output power of 28.3dBm and 26.7dBm with peak drain efficiency of 35.3% and 25.3% for the 2.4GHz and 5GHz bands, respectively. By utilizing multiple fully self-contained linearization algorithms, an EVM of −25dB is achieved at 22.4dBm for the 2.4GHz band and 20.5dBm for the 5GHz band while transmitting 54Mbs OFDM. The chip is fabricated in standard 65nm CMOS and the PAs occupy 0.31mm2 (2.4G) and 0.27mm2 (5G) area.

A 65nm CMOS 2.4GHz 31.5dBm power amplifier with a distributed LC power-combining network and improved linearization for WLAN applications

A linear transconductance stage with process insensitive gain control and gain insensitive output offset current is proposed. A calibration scheme to remove the LO feedthrough (LOFT) and I/Q imbalance is also introduced. The prototype achieves 3rd-order IMD suppression better than 52dBc, LOF suppression better than 32dBc, and image rejection better than 46dBc for all gain settings. The transmit chain achieves an 802.11a EVM of < -40dB

Fully integrated dual-band power amplifiers with on-chip baluns in 65nm CMOS for an 802.11n MIMO WLAN SoC

A fully monolithic 2 times 2(2 times 5 GHz-band, 2 times 2.4 GHz-band) power amplifier (PA) implemented in a 0.18 mum Silicon Germanium (SiGe) HBT process has been developed for a dual band MIMO 802.11n WLAN system. In order to achieve the required performance for the 5 GHz band while maintaining a high level of integration, different approaches have been investigated. A special Through-Wafer-Via (TWV) process on Si wafer was developed and utilized for this 2 times 2 PA. From fabricated 2 times 2 chip measurement results, both 5 GHz-band and 2.4 GHz-band PAs show above 17 dBm linear power output for -28 dB EVM and more than 18 dBm with >14% efficiency for 5 GHz-band and 19% efficiency for 2.4 GHz-band at -25 dB EVM linear output.

A Highly Linear Direct-Conversion Transmit Mixer Transconductance Stage with Local Oscillation Feedthrough and I/Q Imbalance Cancellation Scheme

A fully integrated CMOS direct-conversion 5 GHz transceiver is implemented in a 0.18 /spl mu/m digital CMOS process and housed in an LPCC-48 package. This chip, along with a companion baseband chip, provides a complete 802.11a solution covering all of the world-wide 4.92-5.845 GHz bands. The receiver achieves a 3.5 dB NF while the transmitter achieves a +23 dBm saturated output power. The integrated PA utilizes a linearization technique to allow for high efficiency while maintaining the linear operation required by QAM64 OFDM signals. The transceiver achieves low cost and high yield through the use of various integrated self-contained or system level calibration techniques.