Ali Anvar

Temperature dependence of soft-error rates for FF designs in 20-nm bulk planar and 16-nm bulk FinFET technologies

Alpha particle-induced flip-flop soft-error rates (SER) for 20-nm bulk planar and 16-nm bulk FinFET technologies are characterized over temperature with different supply voltages. Experimental results indicate that the 16-nm FinFET SER changes insignificantly with temperature while the 20-nm planar SER increases by ~2x over the same temperature range. 3D TCAD and circuit-level simulations show changes in single-event transient (SET) pulse width and logic gate delay are the controlling factors, with opposing influences on SER.

Bias Dependence of Single-Event Upsets in 16 nm FinFET D-Flip-Flops

With fabrication processes migrating from planar devices to FinFETs, the differences in physical structure necessitate evaluating the SEU mechanisms of FinFET-based circuits. Since FinFET-based bi-stable circuits have shown better stability at low supply voltages and hence improved power dissipation, it is also necessary to assess the SEU performance over a range of voltages. In this work, the SEU cross section of FinFET-based D-flip-flops was measured with alpha particles, protons, neutrons, and heavy-ions. Results show a strong exponential increase in the SEU rate with reduction in bias for low-LET particles. Technology Computer Aided Design (TCAD) simulations show that the weak variation of collected charge with supply voltage, combined with the standard bias dependence of critical charge, is responsible for this trend.

Angular Effects of Heavy-Ion Strikes on Single-Event Upset Response of Flip-Flop Designs in 16-nm Bulk FinFET Technology

Radiation particles are incident on an integrated circuit (IC) from all angles. For planar technologies, angular incidence increases the deposited charge in a given volume, resulting in higher collected charge at a node and more transistors collecting charge due to increased charge sharing. For FinFET technologies, the physical structure of a FinFET is very different from that of a planar transistor. As a result, deposited and collected charge at a node for angular incidences will be different from what has been published for planar technologies. 3D TCAD simulations and heavy-ion experiments were carried out to investigate the angular effects on flip-flop (FF) single-event upsets (SEU) at the 16-nm bulk FinFET technology. Results show different SEU cross-section trends for the FinFET technology compared to planar technologies. Results show increased upset probability and SEU cross-sections with increasing tilt angles, but those are reduced with increasing roll angles for low-LET heavy-ion incidence. The main reason for this behavior is posited to be variations in charge track length within active Si regions.