Ali Assi

Reduction of EMI through switching frequency dithering

In this paper, a method is presented to reduce electro-magnetic emissions in AC drives. This method is applicable to many AC drives. It is proposed to dither the switching frequency of the power devices of the inverter in a pseudo-random way to spread out the emitted radio- frequency (RF) energy over larger frequency range. The proposed method requires only software changes. Practical constraints to implement the frequency dithering approach are discussed. Simulation & measurements shows an improvement of more than 10 dB. The proposed method also converts certain spikes at integer harmonics of the switching frequency from narrow band to broadband noise.

An offset compensated and high-gain CMOS current-feedback op-amp

This work describes a new CMOS current-feedback operational amplifier (CFOA) with an on-chip continuous-time current-mode input offset voltage compensation circuit. The proposed compensation method is based on a combination of two techniques: the error integration and the current feedback. In addition, this method is irrespective of process and temperature parameters because of its fully symmetrical architecture. HSPICE simulations of the designed CMOS CFOA layout show that the input offset voltage could be reduced to lass than 1 mV, and a gain of around 112 dB and a power consumption of less than 3 mW are achievable.

An efficient estimation of the ROBDD's complexity

This paper describes a new mathematical model for the estimation of reduced ordered binary decision diagrams (ROBDDs) complexity, for any Boolean function with different degrees of variables complexity. The model is capable of predicting the maximum possible ROBDD complexity for Boolean functions with given number of variables. The proposed model is also capable of predicting the number of product terms in the Boolean function that will correspond to the maximum complexity of the ROBDD. This mathematical model works for any type of variable reordering method, and will enable the system performance to be analyzed without building the ROBDD. Since ROBDD complexity can be predicted without building it, a great reduction in terms of time complexity for VLSI CAD designs can be achieved and very useful clues to tackle ROBDD optimization problems in the design of digital circuits can also be obtained.

New sampling method to improve the SFDR of time-interleaved ADCs

Modern communication systems need high-speed ADCs with wide spurious-free dynamic range (SFDR). Conventional time-interleaved ADCs suffer from spurious components that seriously affect the SFDR. Improvement in the SFDR has been achieved by randomizing the samples of the analog input between the different ADC channels at the expense of adding more ADCs and more analog circuitry to the architecture, which increases the complexity of the system as a whole. In this paper, we present the mathematical background describing the effect of randomizing the samples among the interleaved ADCs and we propose a digitally oriented method, based on this analysis, to randomize the mismatches among the ADC channels. Analysis and behavioral simulations show the effectiveness of the proposed approach in multi-channel ADCs with arbitrary bit resolution and sampling rate. For a 10 bit 500 MS/sec ADC, the SFDR achieved using the proposed randomizing method can be as wide as -79 dBc, which is an enhancement of more than 30 dB compared to the conventional time interleaved ADC.

Field programmable Gm-C array for wide frequency range bandpass filter applications

A new programmable bandpass filter approach is presented. It is based on an array of fully differential transconductance circuits to control the filter parameters. The signal path does not contain any switch and fine-tuning of the filter parameters is implemented using programmable capacitors. The filter circuit is based on a biquadratic topology and designed with CMOS 0.18 /spl mu/m technology. SpectreS simulation results show a power consumption less than 5.2 mW with a /spl plusmn/ 0.9 V power supply. In addition, a wide frequency range (10-126 MHz) is achieved. The quality factor can also be tuned from 0.1 to 10.6.

A new time-interleaved architecture for high-speed A/D converters

Time-interleaved ADCs (TIADCs) are among the fastest architectures adopted when speed is the bottleneck of the system. Real-time medical imaging and networked video are few examples of many applications using such fast ADCs. The spurious-free dynamic range (SFDR) is an important parameter of high-speed TIADCs. We propose a new time-interleaved ADC architecture that reduces the spurious components and allow us to obtain better SFDR with reasonable addition of control and delay circuits to the ADC. The proposed architecture is digitally oriented, i.e. does not need complex analog circuitries. Matlab simulations show the effectiveness of the proposed approach in a multichannel ADC with arbitrary bit resolution and sampling rate. For a 12 bit ADC, the SFDR achieved using the proposed randomizing method can be as wide as -78 dBc.

High Performance CMOS Transconductor for Mixed-Signal Analog-Digital Applications

This paper describes a CMOS building block dedicated to high performance mixed analog-digital circuits and systems. The circuit consists of six MOS transistors realizing a new wideband and tunable transconductance. The theory of operation of this device is presented and the effects of transistor nonidealities on the global performances are investigated. Use of the proposed circuit to realize tunable functions (Gm-C filter and current opamp) is illustrated. HSPICE simulations show a wide tuning range of the transconductance value from 40 μS to 950 μS (500 μS) for ±2.5 V (±1.5 V) supply voltages. The transconductance value remains constant up to frequencies beyond 500 MHz. The bandpass filter built with few transconductance blocks and capacitances was simulated with ±2.5 V supply voltage, the center frequency is tunable in the range of 30 MHz to 110 MHz. However, the opamp, which is designed with a transresistance-transconductance architecture, was simulated with ±1.5 V supply voltage. The gain of the opamp can be tuned between 70 dB and 96 dB and high gain-bandwidth product of 145 MHz has been achieved at power consumption of less than 0.5 mW. Experimental results on a fabricated transconductor chip are provided.

Mathematical model to predict the number of nodes in an ROBDD

This paper analyses and describes the relation between the size of a Boolean function and the number of nodes in its ROBDD representation. Knowing the number of variables and the number of product terms of a Boolean function, we can predict the number of nodes in its reordered binary decision diagram (ROBDD) without building the BDD. A mathematical model for this prediction has been developed. This model can be used to find the maximum number of nodes that can be produced for a given number of variables. The model can also be used to find the number of product terms above which the ROBDD is reduced to 1 node only. We demonstrate that the predictions using this model are quite promising, fast and easy to implement.

A fully differential and tunable CMOS current mode opamp based on transimpedance-transconductance technique

A fully differential and tunable CMOS current opamp is described in this paper. This opamp is based on a transimpedance-transconductance circuit technique. The use of a tunable transconductance block results in a voltage-tunable current op amp. Simulation results demonstrate a high-gain which can be tuned between 70 dB and 96 dB. A high gain-bandwidth product of 145 MHz has been achieved at power consumption of less than 0.5 mW and power supply voltage of /spl plusmn/1.5 V.

A new CMOS tunable transconductor dedicated to VHF continuous-time filters

A new CMOS transconductance (Gm) circuit with voltage-tunability and very wide bandwidth is proposed and analysed. The transconductance circuit is then used to realize a tunable VHF 2nd-order bandpass filter cell. The center frequency (f0) of the designed filter can be tuned by varying the transconductance value (gm) of the tunable Gm circuit. Simulation results indicate the excellent performances of both the transconductance circuit and the filter over a wideband range. The transconductance value can be tuned from 40 /spl mu/S to 950 /spl mu/S (490 /spl mu/S) and the filter center frequency (f0) in the range 30 MHz (4 MHz)-110 MHz (49 MHz) for /spl plusmn/2.5 V (/spl plusmn/1.5 V) supply voltages.