P. W. Chandana Prasad

An efficient estimation of the ROBDD's complexity

This paper describes a new mathematical model for the estimation of reduced ordered binary decision diagrams (ROBDDs) complexity, for any Boolean function with different degrees of variables complexity. The model is capable of predicting the maximum possible ROBDD complexity for Boolean functions with given number of variables. The proposed model is also capable of predicting the number of product terms in the Boolean function that will correspond to the maximum complexity of the ROBDD. This mathematical model works for any type of variable reordering method, and will enable the system performance to be analyzed without building the ROBDD. Since ROBDD complexity can be predicted without building it, a great reduction in terms of time complexity for VLSI CAD designs can be achieved and very useful clues to tackle ROBDD optimization problems in the design of digital circuits can also be obtained.

Applicability of feed-forward and recurrent neural networks to Boolean function complexity modeling

In this paper, we present the feed-forward neural network (FFNN) and recurrent neural network (RNN) models for predicting Boolean function complexity (BFC). In order to acquire the training data for the neural networks (NNs), we conducted experiments for a large number of randomly generated single output Boolean functions (BFs) and derived the simulated graphs for number of min-terms against the BFC for different number of variables. For NN model (NNM) development, we looked at three data transformation techniques for pre-processing the NN-training and validation data. The trained NNMs are used for complexity estimation for the Boolean logic expressions with a given number of variables and sum of products (SOP) terms. Both FFNNs and RNNs were evaluated against the ISCAS benchmark results. Our FFNNs and RNNs were able to predict the BFC with correlations of 0.811 and 0.629 with the benchmark results, respectively.

Effect of Quine-McCluskey simplification on Boolean space complexity

The minimization of logic gates is needed to simplify the hardware design area of programmable logic arrays (PLAs) and to speed up the circuits. The VLSI designers can use minimization methods to produce high speed, inexpensive and energy-efficient integrated circuits with increased complexity. Quine-McCluskey (Q-M) is an attractive algorithm for simplifying Boolean expressions because it can handle any number of variables. This paper describes a new model for the estimation of circuit complexity, based on Quine-McCluskey simplification method. The proposed method utilizes data derived from Monte-Carlo simulations for any Boolean function with different count of variables and product term complexities. The model allows design feasibility and performance analysis prior to the circuit realization.

Using Recurrent Neural Networks for Circuit Complexity Modeling

Being able to model the complexity of Boolean functions in terms of number of nodes in a binary decision diagram can be quite useful in VLSI/CAD applications. Our investigation showed that it is possible to use the recurrent neural network (RNN) models for the prediction of circuit complexity. The modeling results matched closely with simulations with an average error of less than 1 %. The correlation coefficient between RNNs predictions and actual results for ISCAS benchmark circuits was 0.629.

A review of security implications and possible solutions for mobile agents in e-commerce

The term e-commerce (or e-business) is used to refer business activities over the internet. Mobile agents (MA) are software entities that can migrate across the network (hence mobile) representing users in various tasks (hence agents). There are many practical benefits of using MA technology especially for e-commerce applications. However, it has also made systems vulnerable to attacks. The trustworthiness of mobile agents is crucial to the success of its application in e-business. To be trustworthy, a mobile agent must protect its gathered data against adversaries encountered while traversing the Internet. This paper focuses on examining the conditions under which vulnerabilities are created and looks at the security technology that can be used for deploying MA for heterogeneous environments in general and MA for ecommerce in particular.

A neural model for processor-throughput using hardware parameters and software's dynamic behavior

Design space exploration of a processor system, prior to its hardware implementation, usually involves cycle-accurate simulations. The simulations provide a good measure of performance but require long periods of time even when a small set of design variations are assessed. An alternative is to use empirically-developed models which are much faster than actual simulations. In this paper, we have proposed an NN model for processor performance (IPC) prediction. The model uses a larger set of input parameters (especially the software parameters) than the prior models. For dimension reduction, we found PCA to be a more useful technique than correlation and graphical analysis. For the purpose of training the NNs, we used the data from a large number of simulations of industry-standard SPEC CPU 2000 and SPEC CPU 2006 benchmark suites In order to collect the NN training data in a reasonable period of time, we utilized two well-known techniques, namely, benchmark-subsetting and SPs.

Prediction of area and length complexity measures for binary decision diagrams

Measuring the complexity of functions that represent digital circuits in non-uniform computation models is an important area of computer science theory. This paper presents a comprehensive set of machine learnt models for predicting the complexity properties of circuits represented by binary decision diagrams. The models are created using Monte Carlo data for a wide range of circuit inputs and number of minterms. The models predict number of nodes as representations of circuit size/area and path lengths: average path length, longest path length, and shortest path length. The models have been validated using an arbitrarily-chosen subset of ISCAS-85 and MCNC-91 benchmark circuits. The models yield reasonably low RMS errors for predictions, so they can be used to estimate complexity metrics of circuits without having to synthesize them.

Improved Variable Ordering for ROBDDs

Present here is a novel algorithm for minimization of the Reduced Ordered Binary Decision Diagram (ROBDD) by finding the best variable ordering for any Boolean function. Selection of ordering relation is achieved by considering each sub functions.

Variable Order Verification Use of Logic Representation

Boolean functions are fundamental to synthesis and verification of digital logic, and compact representations of Boolean functions have great practical significance. Conversion between those representations is common, especially when one is used to represent the input and another speeds up relevant algorithms. In the last 15 years, a number of applications based on efficient manipulation of Boolean functions gained industrial significance, notably in automated design and verification of logic circuits. The efficient representation and manipulation of Boolean functions is important for many algorithms in a wide variety of applications in particular, many problems in computer-aided design for digital circuits (CAD). The efficiency of the Boolean manipulation depends on the form of representation of the Boolean function. It is unavoidable and important problem to find a variable ordering which minimize the size of a BDD, since variable ordering has a great influence on the computation time and storage requirements for Boolean function manipulation number of times each variable takes part in the Logic operation to obtain the best possible the variable order. This paper describes a technique for finding the best variable ordering by analyzing the logic gate representation in the given Boolean function. Algorithm starts with initial variable ordering. The system will check each sub expression to find out the number times each variable takes part in each type of logic operations. The number of occurrences for each variable will be stored and then all the totals are arranged in descending order to identify the variable ordering for that Boolean function. If more than one input variables have the same total then a special criteria will be used to break the tie: We present graph-based evidence of the improvement obtained by using highly effective logical verification based variable ordering technique for BDDs. It is shown that the effectiveness of the Decision Diagram is mainly depending on the variable ordering selected. It is not practical to have any unique ordering for a given Boolean function and it can be selected among the number of best results, what will be more appropriate with the design. This new technique, easy to implement and automate, consistently creates high quality variable ordering for Boolean function.