Alice Wang

A 120nW 18.5kHz RC oscillator with comparator offset cancellation for ±0.25% temperature stability

Integrated low-frequency oscillators can replace crystal oscillators as sleep-mode timers to reduce the size and cost of wireless sensors [1]. Since the timer is one of the few continuously functioning circuits, minimizing its power consumption can greatly reduce sleep-mode power of highly duty-cycled systems. Temperature stability of the oscillator is important in order to minimize timing uncertainly and guard time for the radios, and thus maximizing sleep time. The voltage-averaging feedback method described in [2] achieves high stability in the MHz frequencies, but when scaled to the kHz range, requires very large filters. On the other extreme, gate leakage-based timers have been designed for sub-nW power consumption, but operate in the sub-Hz frequencies [3]. In the past, high accuracy RC oscillators in the kHz range have been designed with feed-forward correction [1] and self-chopped operation [4]. In this work, an offset cancellation architecture achieves long-term frequency stability and temperature stability while operating at lower power.

10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor

Driven by consumer demand, mobile devices such as smartphones and tablets are offering more desktop-like capabilities. High-performance CPUs and GPUs, which handle compute-intensive tasks, are key to enhancing the user experience in applications such as 3D gaming, high-definition video and internet browsing. A CPU and GPU on a tablet device, however, can together consume up to 90% of the total SoC power. As the number of CPU and GPU cores on mobile devices continues to grow, it will require innovation to keep within fixed power and thermal budgets, while providing high performance.

23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques

This paper describes the high-performance CPU design of a heterogeneous octa-core CPU complex, incorporated into a highly integrated mobile SoC for smartphone applications. The SoC is fabricated in a 28nm high-x metal-gate CMOS, and has a die size of 89mm2. Cu pillars are used for the die-to-substrate interface with fine substrate trace pitch. The SoC is packaged in a 14mmx14mm, 832 ball, 0.4mm pitch BGA. An integrated cellular modem supports rei. 9, cat. 4 LTE (FDD and TDD), while additional cellular and RF connectivity includes DC-HSPA+, TD-SCDMA, EDGE, 802.11ac, Bluetooth LE, multi-GNSS (GPS, GLONASS, Beidou, Galileo & QZSS), and ANT+. Multimedia features are highlighted by a high-performance Power-VR Series6 GPU, support for WQXGA displays (2560×1600), a 20Mpixel image processor and camera interface, and ultra-HD video playback support for H.264 and VP9.

Through the Looking Glass II?Part 1 of 2: Trend Tracking for ISSCC 2013 [ISSCC Trends]

The intent of the second part of this article is to share a sampling of the views held by the diverse group of experts represented by the International Solid-State Circuits Conference (ISSCC) 2013 Energy Efficient Digital; High Performance Digital; Technology Directions; Imagers, MEMS, Medical, and Displays (IMMD); and Memory program subcommittees. We published the findings of the subcommittees on Analog, Data Converters, RF, Wireline, and Wireless subcommittees in the Winter 2013 issue of this magazine.

An RC Oscillator With Comparator Offset Cancellation

A fully-integrated 18.5 kHz RC time-constant-based oscillator is designed in 65 nm CMOS for sleep-mode timers in wireless sensors. A comparator offset cancellation scheme achieves 4× to 25× temperature stability improvement, leading to an accuracy of ±0.18% to ±0.55% over -40 to 90 °C. Sub-threshold operation and low-swing oscillations result in ultra-low power consumption of 130 nW. The architecture also provides timing noise suppression, leading to 10× reduction in long-term Allan deviation. It is measured to have a stability of 20 ppm or better for measurement intervals over 0.5 s. The oscillator also has a fast startup-time, with the period settling in 4 cycles.

Out of Thin Air: Energy Scavenging and the Path to Ultralow-Voltage Operation

In recent years there has been much interest in and progress toward the design of energy efficiency systems. The ultimate vision is to operate electronic circuits from ambient energy (see Figure 1). Gene Frantz, a pioneer in signal processing architectures and systems, has driven the vision of ultralow-power electronics. To continue scaling the energy per operation, Gene has proposed a number of concepts, from the use of new signaling and computing schemes to ultralow-voltage (ULV) design, multicore signal processors, and new computational substrates. He has also outlined the critical components of an energy-harvesting system, including the notion of an energy buffer. This article addresses one critical aspect of ultralow-power electronics: ULV design, along with the required support structures.

4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance

This paper describes design features of the high-performance CPU from a heterogeneous tri-cluster, deca-core CPU subsystem incorporated into the Helio X20 mobile SoC for smartphone applications. The SoC is fabricated in a 20nm high-κ metal-gate CMOS, and has a die size of 100mm2. Additional key features of the SoC include: a graphics processor unit, multimedia (including 32MPixel/24fps camera support), and connectivity subsystems integrating 802.11ac, GPS, and multistandard cellular modems, featuring LTE FTD/TDD R11 Cat-6 with 20+20 carrier aggregation (300/50Mb/s) DC-HSPA+, TD-SCDMA, Edge, CDMA2000 1x/EVDO Rev. A (SRLTE).

3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance

This paper describes logic and circuit design features of a heterogeneous tri-cluster deca-core CPU complex incorporated into a 10nm FinFET mobile SoC for smartphone applications. Similar to Helio X20 [1], the Deca-Core compute function contains three separate clusters of ARMv8a CPUs. The high-performance (HP) cluster is updated to incorporate the most power-efficient out-of-order Cortex-A73 CPU, operating at max frequency of 2.8GHz. In X20, the low-power (LP) and ultra-low power (ULP) clusters used Cortex-CA53 with different implementation flows, while this work achieves a +44% more power-efficient ULP solution based on the newer Cortex-CA35 CPU (Fig. 3.4.1). In addition, the LP cluster achieves a +36% more performance than ULP or +40% more power-efficiency than the HP cluster, for optimal sustainable performance/power applications including augmented reality and virtual reality (AR/VR). A die photograph, Fig. 3.4.7, highlights the three CPU clusters.

A vertical solenoid inductor for noise coupling minimization in 3D-IC

This paper presents the use of an integrated solenoid inductor in three dimensional integrated circuits (3D-IC) for improved noise mitigation. The structure is fabricated in a two-tier, stacked 28nm CMOS using through silicon vias (TSV). The structure is implemented as part of an LC voltage-controlled oscillator (VCO), and exhibits 6dB improvement in phase noise and 14dB less coupling from adjacent digital clock lines compared to a planar two-turn inductor.

Digital Circuits for Mobile Computing: Optimizing Power Performance and Innovation Opportunities

Todays mobile phone has millions of times more computing power than all of the NASA computers that put two astronauts on the moon. It is through the progress made by Moores law and the ability of software engineers to take advantage of increased computing to create new applications that help our daily life be more efficient. There is enough computational power available that we are at the precipice of intelligent robots, autonomous vehicles, and machine learning for a smart home/environment/life.