Sumanth Gururajarao

A 65-nm Mobile Multimedia Applications Processor with an Adaptive Power Management Scheme to Compensate for Variations

In this paper we present the SmartReflextrade power management techniques implemented on the OMAP3430 Mobile Multimedia Applications Processor. By using multiple voltage domains, fine grain power domains, split-rail memories, and adaptive compensation, SoC active power reduction of 66% and leakage power reduction of 2~3 orders of magnitude was achieved. OMAP3430 contains more than 150M transistors.

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques

System on Chip (SoC) integration is the theme of the first integrated 3.5G baseband and multimedia applications processor fabricated using a low-power digital and analog design platform and 45nm process technology. This SoC supports mobile standards: HSUPA/HSDPA, WCDMA, EDGE/GPRS/GSM and applications such as MPEG-4 video streaming, Java and MP3 audio. The high- performance multimedia, multiprocessor engine includes an 840MHz ARM1176, a 480MHz TMS320C55x DSP, and a 240MHz image processor.

SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors

In the last couple of decades, handheld wireless devices such as cell phones have become one of the most prolific electronic devices in history. With this has come an exploding demand for performance and features that cover almost every aspect of our digital multimedia interconnected lives including 3-D gaming, still and video cameras, WAN, Bluetooth, high-speed data connections, and so on. As ever increasing features continue to be integrated into these products, there is an ongoing need to develop innovative ways to reduce power consumption and extend battery life. Only through continual process and circuit cooptimization are we able to reap the benefits of technology scaling required to meet the feature and performance demands in the face of increasing process variations and exponentially increasing leakage currents. As a result, SmartReflex power and performance technologies have been developed and applied to 90 nm, 65 nm, and 45 nm system-on-chip (SoC), to achieve optimal power and performance. SmartReflex technologies consist of two major components to optimize SoC power and performance: static and dynamic techniques. Static techniques like power-gating, retention and off-mode are used to lower leakage and allow for extended battery lifetimes for standby times. Dynamic techniques such as dynamic power switching, adaptive voltage scaling, dynamic voltage/frequency scaling with split-rail memories, and adaptive body-biasing address active power and performance challenges. These techniques enable SoC solutions with the performance of the latest process technology and provide the user with advanced multimedia features with orders of magnitude of power reduction.