Hugh Thomas Mair

23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques

This paper describes the high-performance CPU design of a heterogeneous octa-core CPU complex, incorporated into a highly integrated mobile SoC for smartphone applications. The SoC is fabricated in a 28nm high-x metal-gate CMOS, and has a die size of 89mm2. Cu pillars are used for the die-to-substrate interface with fine substrate trace pitch. The SoC is packaged in a 14mmx14mm, 832 ball, 0.4mm pitch BGA. An integrated cellular modem supports rei. 9, cat. 4 LTE (FDD and TDD), while additional cellular and RF connectivity includes DC-HSPA+, TD-SCDMA, EDGE, 802.11ac, Bluetooth LE, multi-GNSS (GPS, GLONASS, Beidou, Galileo & QZSS), and ANT+. Multimedia features are highlighted by a high-performance Power-VR Series6 GPU, support for WQXGA displays (2560×1600), a 20Mpixel image processor and camera interface, and ultra-HD video playback support for H.264 and VP9.

4.3 A 20nm 2.5GHz ultra-low-power tri-cluster CPU subsystem with adaptive power allocation for optimal mobile SoC performance

This paper describes design features of the high-performance CPU from a heterogeneous tri-cluster, deca-core CPU subsystem incorporated into the Helio X20 mobile SoC for smartphone applications. The SoC is fabricated in a 20nm high-κ metal-gate CMOS, and has a die size of 100mm2. Additional key features of the SoC include: a graphics processor unit, multimedia (including 32MPixel/24fps camera support), and connectivity subsystems integrating 802.11ac, GPS, and multistandard cellular modems, featuring LTE FTD/TDD R11 Cat-6 with 20+20 carrier aggregation (300/50Mb/s) DC-HSPA+, TD-SCDMA, Edge, CDMA2000 1x/EVDO Rev. A (SRLTE).

3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance

This paper describes logic and circuit design features of a heterogeneous tri-cluster deca-core CPU complex incorporated into a 10nm FinFET mobile SoC for smartphone applications. Similar to Helio X20 [1], the Deca-Core compute function contains three separate clusters of ARMv8a CPUs. The high-performance (HP) cluster is updated to incorporate the most power-efficient out-of-order Cortex-A73 CPU, operating at max frequency of 2.8GHz. In X20, the low-power (LP) and ultra-low power (ULP) clusters used Cortex-CA53 with different implementation flows, while this work achieves a +44% more power-efficient ULP solution based on the newer Cortex-CA35 CPU (Fig. 3.4.1). In addition, the LP cluster achieves a +36% more performance than ULP or +40% more power-efficiency than the HP cluster, for optimal sustainable performance/power applications including augmented reality and virtual reality (AR/VR). A die photograph, Fig. 3.4.7, highlights the three CPU clusters.

Digital Circuits for Mobile Computing: Optimizing Power Performance and Innovation Opportunities

Todays mobile phone has millions of times more computing power than all of the NASA computers that put two astronauts on the moon. It is through the progress made by Moores law and the ability of software engineers to take advantage of increased computing to create new applications that help our daily life be more efficient. There is enough computational power available that we are at the precipice of intelligent robots, autonomous vehicles, and machine learning for a smart home/environment/life.

Session 17 overview: SRAM

Advanced SRAM continues to be one of the critical technology enablers for a wide range of applications - from mobile to high performance servers to the Internet of Everything. Combining the process technologies of FinFET and FD-SOI with advanced circuit techniques enables high-performance, low-voltage, and low-power applications. This session highlights 10nm FinFET technology with the smallest bitcell achieved to date for SRAM at 0.04µm2. Area efficient 8T SRAMs are demonstrated in 14nm FinFET technology by adopting small signal sensing to enable longer bitlines. FD-SOI is utilized by researchers in applying Razor techniques to SRAM.

Session 13 overview: Advanced embedded memory: Memory subcommittee

Embedded memory continues to be a critical technology enabler for a wide range of applications from high-performance computing to mobile applications. This years conference highlights significant increases in on-chip capacity and bandwidth along with a continued drive towards advanced technology nodes while maintaining a strong focus on low-power operation. A 1Gb embedded DRAM using 22nm tri-gate CMOS logic technology is presented to meet the demands of bandwidth-intense applications. Papers in 14nm FinFET, 16nm FinFET, and 20nm planar technologies demonstrate state-of-the-art read/write assist techniques in order to challenge V MIN limitations. Various aspects of power and performance optimizations are highlighted in the session, including leakage power, dynamic power, latency, and throughput.