Alinaghi Marzoughi

Investigation and design of modular multilevel converter in AFE mode with minimized passive elements

This paper investigates design procedure of modular multilevel converter (MMC) in active front-end (AFE) mode of operation. The design in performed trying to minimize the amount of passive elements including arm inductances and submodule capacitances. This has been done using basic controllers needed for operation of MMC in AFE mode, without employing any additional controller in the circuit. In other words, the design is taking advantage of properly locating arm inductance and submodule capacitance magnitudes with respect to intrinsic resonance phenomenon in MMC converter. A model is developed in MATLAB/Simulink environment in order to show feasibility of the proposed design and also to have a comparison between the proposed MMC AFEs and the formal designs. The comparison in case of the shown case study reveals 90% reduction in arm inductance magnitude and 40% reduction in submodule capacitance values at the expense of adding filter inductaces with much smaller size.

Steady-state analysis of voltages and currents in modular multilevel converter based on average model

Modular multilevel converter (MMC) is being considered as the next generation converter among multilevel topologies and by introduction of MMC, a new era has opened to the field of medium- and high-voltage, high-power converters. Sizing the passive elements and design of the converter and its performance evaluation is thus of great importance for researchers in this area. The present paper performs a steady-state analysis of the modular multilevel converter (MMC) based on average model. The magnitudes and phase angles of current and voltage quantities are calculated. The equations are solved for different components of the circulating current and submodule voltage, and the resonance behavior in circulating current harmonics is investigated. Based on resonance behavior of circulating current harmonics, a guideline is given to choose the magnitude of submodule capacitance and arm inductance. A model is developed in MATLAB/Simulink environment in order to verify accuracy of the calculations done.

Characterization and comparison of latest generation 900-V and 1.2-kV SiC MOSFETs

This paper performs static and dynamic performance characterization of latest generation 900-V and 1.2-kV discrete Silicon Carbide (SiC) MOSFETs from four well-known manufacturers: CREE, ROHM, General Electric (GE) and Sumitomo Electric Industries (SEI). The static characterization performed includes acquisition of output characteristics, transfer characteristics, specific on-state resistances, threshold voltages and junction capacitances of the devices under test (DUTs). The static characterizations are done from 25°C up to 150°C to investigate variation of parameters versus temperature. At the other hand and for dynamic characterization, following a double-pulse tester design the tests are done at four different temperatures on all devices: 25°C, 100°C, 150°C and 200°C. In dynamic test, recommended gate voltages are applied to all devices and the switching speeds are matched. The switching losses are computed from double-pulse test (DPT) results.

Design and comparison of cascaded H-bridge, modular multilevel converter and 5-L active neutral point clamped topologies for drive application

This paper investigates the design procedure of cascaded H-bridge (CHB), modular multilevel converter (MMC) and five-level active neutral point clamped (5-L ANPC) topologies for medium-voltage and high-power industrial motor drive application. The design is performed using 1.7-kV insulated gate bipolar transistor (IGBT) technology for CHB and MMC converters, and utilizing 3.3- and 4.5-kV IGBTs for 5-L ANPC topology. When designing the converters, the effect from leakage parameters of the multi-pulse transformer used together with the diode front-end rectifier stage is taken into account via a model. Also comparison is done between the designed converter topologies at three different voltage levels: 4.16-, 6.9- and 13.8-kV (only first two voltage levels in case of 5-L ANPC) and three different power levels: 1-, 3- and 5-MVA. The comparison is done from several points of view like capacitance requirements, diode front-end and inverter stage losses, semiconductor rating, semiconductor die size and parts count.

Characterization and Evaluation of the State-of-the-Art 3.3-kV 400-A SiC MOSFETs

Since their introduction, the SiC-based semiconductors have been of special interest to the field of power electronics, enabling increase in system efficiency, maximum operating temperature, and power density. In higher voltage range, these semiconductors are at early stage of development and yet are not commercialized. This paper investigates state-of-the-art noncommercialized 3.3-kV 400-A full-SiC MOSFETs where for the first time such MOSFETs are thoroughly characterized and their performance is evaluated and compared against similar rating Si counterparts. Extensive static and dynamic characterizations are done with emphasize on enabling conduction and switching loss calculation in any target application. I–V curves for MOSFET and Shottky-barrier diode (SBD), RDSon, C–V curves and threshold voltages are addressed by measurement at different temperatures. Moreover, the SiC MOSFETs are tested in chopper circuit with an inductive load for measurement of switching losses. This is done at 2-kV bus voltage from 50 up to 400 A load current. Finally, simulations are done in MATLAB/Simulink to evaluate the performance of 3.3-kV 400-A modules in medium-voltage high-power industrial drive application. The case study shows advantages of the 3.3-kV SiC MOSFET technology over 3.3-kV Si IGBTs and 1.7-kV SiC MOSFETs from efficiency, installed die area and power density points of view.

Analysis of capacitor voltage ripple minimization in modular multilevel converter based on average model

This paper investigates reduction of submodule voltage ripple in modular multilevel converter (MMC). The reduction is achieved by injecting the optimum amount of circulating current across the phase leg of the converter. The magnitude and phase angle of arm currents and submodule voltage quantities are calculated via an average model derived for the MMC topology. Then based on the derived equations for submodule voltage components at different ac frequencies, an effort is done to calculate and inject the optimum magnitude of circulating current in order to minimize the voltage fluctuation across submodule capacitors. Also in this paper, the effect of natural and optimized circulating currents on converter losses and efficiency is investigated via calculating semiconductor losses.

Power Electronics Building Block (PEBB) design based on 1.7 kV SiC MOSFET modules

This paper presents the design of a Power Electronics Building Block (PEBB) based on 1.7 kV SiC MOSFET power modules. The PEBB is an H-bridge converter module that can be cascaded to construct multilevel converters. Novel designs including gate driver with Rogowski shortcircuit protection, powerful distributed controller, isolated A/D sensor with high common-mode noise rejection, double-side cooling mechanical layout have been achieved. The paper begin with the evolution of PEBB architectures and the specifications of the designed PEBB. It then presents detailed design considerations and solutions of all the critical components. Finally, experimental results demonstrate the excellent performance of the individual components and the PEBB as a unity in various operation modes.