Allen C.-H. Wu

A predictive system shutdown method for energy saving of event-driven computation

We present a system-level power management technique for power saving of event-driven applications. We present a new predictive system shutdown method to exploit sleep mode operations for power saving. We use an exponential-average approach to predict the upcoming idle period. We introduce two mechanisms, prediction-miss correction and pre-wakeup, to improve the hit ratio and to reduce the delay overhead. Experiments on four different event-driven applications show that our proposed method achieves high hit ratios in a wide range of delay overheads, which results in a high degree of power saving with low delay penalties.

Scheduling techniques for variable voltage low power designs

This paper presents an integer linear programming (ILP) model and a heuristic for the variable voltage scheduling problem. We present the variable voltage scheduling techniques that consider in turn timing constraints alone, resource constraints alone, and timing and resource constraints together for design space exploration. Experimental results show that our heuristic produces results competitive with those of the ILP method in a fraction of the run-time. The results also show that a wide range of design alternatives can be generated using our design space exploration method. Using different cost/delay combinations, power consumption in a single design can differ by as much as a factor of 6 when using mixed 3.3V and 5V supply voltages.

Essential issues for IP reuse

With widespread recent emphasis on System-On-a-Chip (SOC), IP reuse has emerged as a vital and growing business in semiconductor industry. In this paper, we will address essential issues for IP reuse by discussing current challenges to the success of IP businesses and identifying the obstacles that need to be overcome.

A transformation-based method for loop folding

We propose a transformation-based scheduling algorithm for the problem given a loop construct, a target initiation interval and a set of resource constraints, schedule the loop in a pipelined fashion such that the iteration time of executing an iteration of the loop is minimized. The iteration time is an important quality measure of a data path design because it affects both storage and control costs. Our algorithm first performs an As Soon As Possible Pipelined (ASAPp) scheduling regardless the resource constraint. It then resolves resource constraint violations by rescheduling some operations. The software system implementing the proposed algorithm, called Theda.Fold, can deal with behavioral loop descriptions that contain chained, multicycle and/or structural pipelined operations as well as those having data dependencies across iteration boundaries. Experiment on a number of benchmarks is reported. >

An effective methodology for functional pipelining

The problem of scheduling a loop in a pipelined fashion such that the iteration time (turnaround time) is minimized, given a loop behavior, a target initiation interval, and resource constraints, is considered. The iteration time is an important quality measure of a data path design because of its direct correlation with both the storage and the control costs. The scheduler starts with performing as-soon-as-possible-pipelined (ASAP/sub p/) scheduling without regard to the resource constraint. It then resolves the resource constraint violations, if there are any, by repeatedly rescheduling some operations.<<ETX>>

Layout-area models for high-level synthesis

The authors propose a novel layout area model for quality measures in high-level synthesis. The model is proposed for two commonly used datapath and control layout architectures. Except for macrocells (PLAs), the proposed models formulate layout area as a function of transistors and routing tracks which can be computed in O(n log n) time complexity, where n is the number of nets in the netlist. This allows one to explore design space in high-level synthesis rapidly and efficiently. The authors have tested their layout models on the widely used elliptic-filter benchmark. The results show that these models can more accurately predict layout areas than models based on the number and size of registers and multiplexers.<<ETX>>

Accurate layout area and delay modeling for system level design

The problem of estimating design quality measures to accurately reflect design tradeoffs and efficiently explore the design space is discussed. Specifically, interest is centered on predicting the layout area and delay of a given structural RT level design. Clearly, current RT level cost measures are highly simplified and do not reflect the real physical design. In order to establish a more realistic assessment of layout effects, a layout model which accurately and efficiently accounts for the effects of wiring and floorplanning on the area and performance layout of RT level designs is proposed. Benchmarking has shown that this model is quite accurate.<<ETX>>

A performance and routablity driven router for FPGAs considering path delays

This paper presents a new performance and routability driven router for symmetrical array based Field Programmable Gate Arrays (FPGAs). The objectives of our proposed routing algorithm are twofold: (1) improve the routability of the design (i.e., minimize the maximumrequired routing channel density) and (2) improve the overall performance of the design (i.e., minimize the overall path delay). Initially, nets are routed sequentially according to their criticalities and routabilities. The nets/paths violating the routing-resource and timing constraints are then resolved iteratively by a rip-up-and-rerouter, which is guided by a simulated evolution based optimization technique. The proposed algorithm considers the path delays and routability throughout the entire routing process. Experimental results show that our router can significantly improve routability and reduce delay over many existing routing algorithms.

Combining technology mapping and placement for delay-optimization in FPGA designs

We combine technology mapping and placement into a single procedure, M.Map, for the design of RAM-based FPGAs. Iteratively, M.Map maps several subnetworks of a Boolean network into a number of CLBs on the layout plane simultaneously. For every output node of the unmapped portion of the Boolean network, many ways of mapping are possible. The choice of which mapping to be used depends not only on the location of the CLB into which the output node will be mapped but also on its interconnection with those already mapped CLBs. To deal with such a complicated interaction among multiple output nodes of a Boolean network, multiple ways of mappings and multiple number of CLBs, any greedy algorithm will be insufficient. Therefore, we use a bipartite weighted matching algorithm in finding a solution that takes the global information into consideration. With the availability of the partial placement information, M.Map is able to minimize the routing delay in addition to the number of CLBs. Experimental results on a set of benchmarks demonstrate that M.Map is indeed effective and efficient. >

Timing models for high-level synthesis

A timing model for clock estimation in high-level synthesis is described. In order to obtain realistic timing estimates, the proposed model considers datapath, control and wire delays, and several technology factors, such as layout architecture, technology mapping, buffers insertion and loading effects. The experimental results show that this model can provide much better estimates than previous models. This model is well suited for automatic and interactive synthesis as well as feedback-driven synthesis where performance matrices can be rapidly and incrementally calculated.<<ETX>>