Wen-Jong Fang

Performance-driven multi-FPGA partitioning using functional clustering and replication

This paper presents a new performance-driven partitioning method for multi-FPGA designs. The proposed method consists of three steps: (1) functional-cluster formation, (2) slack computation, and (3) set-covering-based partitioning with functional replication. The proposed method performs multi-FPGA partitioning by taking into account path delays and design structural information. We introduce a functional replication technique which performs circuit replications at the functional-cluster level instead of the cell level for delay and interconnect minimization. Experimental results on a number of benchmarks and industrial designs demonstrate that the proposed method achieves high-performance and high-density multi-FPGA partitions.

A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations

We present a new synthesis and partitioning approach for multiple-FPGA implementations from register-transfer-level (RTL) netlists. Our approach bridges the gap between RTL/logic synthesis and physical partitioning by finely tuning logic implementations suited for multiple-FPGA systems. We propose a hierarchical functional structuring and partitioning method which fully exploits the design structural hierarchy by decomposing RTL components into sets of logic sub-functions. This allows the partitioner to place portions of components into FPGA partitions. Experimental results on a number of benchmarks and industrial designs show that our approach achieves significant improvements in CLB and IO-pin utilizations of FPGAs compared to that produced using a traditional multiple-FPGA partitioning method.

Multiway FPGA partitioning by fully exploiting design hierarchy

In this paper, we present a new integrated synthesis and partitioning method for multiple-FPGA applications. Our approach bridges the gap between HDL synthesis and physical partitioning by fully exploiting the design hierarchy. We propose a novel multiple-FPGA synthesis and partitioning method which is performed in three phases: (1) fine-grained synthesis, (2) functional-based clustering, and (3) hierarchical set-covering partitioning. This method first synthesizes a design specification in a fine-grained way so that functional clusters can be preserved based on the structural nature of the design specification. Then, it applies a hierarchical set-covering partitioning method to form the final FPGA partitions. Experimental results on a number of benchmarks and industrial designs demonstrate that I&slash;O limits are the bottleneck for CLB utilization when applying a traditional multiple-FPGA synthesis method on flattened netlists. In contrast, by fully exploiting the design structural hierarchy during the multiple-FPGA partitioning, our proposed method produces fewer FPGA partitions with higher CLB and lower I&slash;O-pin utilizations.

Preserving HDL synthesis hierarchy for cell placement

We propose an integrated HDL-synthesis and placement method for row-based layouts. Our approach bridges the gap between HDL synthesis and placement by fully utilizing design hierarchy. It jkt synthesizes an HDL design specification into a hierarchy of subcircuits. It then groups subcircuits to form strongly connected macro cells, followed by performing a macrocell placement to determine the location of the macro cells on the layout plane. Finally, it maps the resulting macro-cell placement into a row-based placement and applies a simulated-annealing procedure to refine the row-based placement. Ezperiments on a number of large industry designs demonstrate that the proposed method achieves, on the average, 22% area T&L&On, 18% wire length reduction, and several times of speed up compared to that without the hierarchy information.

A real-time RTL engineering-change method supporting on-line debugging for logic-emulation applications

In recent years, logic emulation has been widely usedas a key design verification methodology in many complex CPU, telecom, and multimedia design projects. When using logic emulation for design verification, designers often need toperform engineering changes as a result of design debugging of a design specificationmodification. One of the essential issues to engineeringchanges is the turn-around time. Ideally, after designers modify their designs, they resume their debugging and verification tasks immediately. However, converting a design from its Register-Transfer-Level (RTL) description to a target emulator is a time-consuming procedure which may take hours. Such long engineering-change turn-around times are unacceptable by the designers. In this paper, we present a real-time RTLengineering-change method supporting on-line debuggingfor logic-emulation applications. We propose a novel design method which is able to link design data generated at different design stages in a unified way. Using thismethod, the users can immediately locate the portion ofthe circuit design affected by the design modification fromits RTL specification. This feature provides users with afast time-to-debug environment by significantly improving the efficiency of the engineering-change process. We have developed aprototype system Quick ECO supporting interactive on-line RTL engineering changes. Experimental results on a number of industrial designs are reported to demonstrate the effectiveness of the proposed method.

Integrating HDL synthesis and partitioning for multi-FPGA designs

The authors examine the interaction of HDL synthesis and multi-FPGA partitioning on designs with varying structural characteristics and HDL coding styles. They demonstrate that an integrated synthesis and partitioning methodology is crucial to achieving high-density designs.

A multi-level FPGA synthesis method supporting HDL debugging for emulation-based designs

Converting an HDL-based design into an emulation system for design verification is an extremely complex and time-consuming task. One possible solution to improve productivity is an effective emulation-based design methodology that exploits the modularity of designs. This paper develops and explores such a methodology. We present a multi-level synthesis method which is able to establish a direct link between High-level Descriptive Language (HDL) constructs and corresponding circuit designs. This feature greatly facilitates HDL debugging capabilities such that when bugs are detected in sub-netlists, links allow the corresponding HDL source code to be easily recognized. This powerful feature greatly reduces design debugging time. Experimental results on a set of industrial designs are reported in order to demonstrate the effectiveness of the proposed synthesis methodology.

EmGen-a module generator for logic emulation applications

Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multiphase design tasks, which is a very time-consuming process. Hence, shortening the time to emulation is always the main concern for the logic-emulation design process. One approach to shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in hardware descriptive languages. Furthermore, the module generator can effectively generate a multiple field-programmable gate array (FPGA) macro for large macros that cannot fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their register transfer-level description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.

Module generation of complex macros for logic-emulation applications

Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design verification. Using an emulator, designers can realize designs through a software configuration process and perform real-time design verification before fabricating the chip into silicon. However, converting designs into an emulator involves the use of multi-phase design tasks, which is a very time-consuming process. Hence, shortening the Time-To-Emulation (TTE) is always the main concern for the logic-emulation design process. One approach t o shorten the design processing time is to replace portions of the design with macro cells. This paper presents a module generator for logic-emulation applications, which is able to generate macro cells of arbitrarily complex functions described in High-level Descriptive Languages the (HDLs), Furthermore, the module generator can effectively generate a multiple-FPGA macro for large macros which can not fit in a single FPGA chip. Experiments using the module generator for logic emulation are reported. The results demonstrate that the module generator can effectively and efficiently generate complex macros from their Register-Transfer-Level (RTL) description. In addition, the results also show that the design processing time is significantly shortened when the module generation method is incorporated into the logic-emulation design flow.

The design and implementation of a cooperative design-view environment for interactive partitioning applications

This paper presents a cooperative design‐view environment for interactive partitioning applications. This environment provides the user with a comprehensive viewing facility that describes the potentially complex relationships between various design objects. Using this environment, the user is able to evaluate and analyse design results visually throughout the entire partitioning process. We have developed a graphical user interface (GUI) environment for the InterPar system which supports mixed automatic and manual partitioning for multiple‐field programmable gate array (FPGA) designs. The preliminary experiments have shown that the use of InterPar may lead to a new direction for the exploration of new partitioning approaches based on the circuit‐structure analysis.