Allen Park

Novel Technique to Identify Systematic and Random Defects during 65 nm and 45nm Process Development for Faster Yield Learning

Advanced bright field inspection tools available today applied on development wafer may often result in 100 k to 1 M defects per wafer. Such defect data consist of systematic and random defects that may be yield limiting or may be just cosmetic issue with low probability of yield impact. It is also difficult to identify systematic defects from random defects by using traditional defect classification method where 50 to 100 defects per wafer are sampled on the SEM review. Missing important systematic defect types can be very costly and cause delays in product introduction. In this paper, a new approach has been introduced to improve identification of systematic defect and to improve defect sampling for SEM review. By applying design data to defect inspection, many of the systematic defects have been identified and monitored for efficient management of systematic defects. Application of design data in defect inspection provides new capability in identifying systematic defects that a traditional random sampling or repeater analysis could not identify. Identification and characterization of an important process related defect type, STI cave defect, is described in this paper to illustrate the new approach. By using the design data to bin defect types, the STI cave defect was identified and quantified. The discovery was further confirmed using SEM review and FIB. An insufficient gap-fill during the deposition step was determined as culprit for this void defect type. The novel technique described here provided a way of detecting and identifying such systematic defect, enabling fab to quickly resolve the issue. Furthermore creating this capability embedded on inspection tool promises to provide a new paradigm in defect inspection technology.

Novel technique to separate systematic and random defects during 65nm and 45nm process development

Defect inspections performed in R&D may often result in 100k to 1M defect counts on a single wafer. Such defect data combine systematic and random defects that may be yield limiting or just nuisance defects. It is difficult to identify systematic defects from defect wafer map by traditional defect classification where random sample of 50 to 100 defects are reviewed on review SEM. Missing important systematic defect types by traditional sampling technique can be very costly in device introduction. Being able to efficiently sample defects for SEM review is not only challenging, but can result in a Pareto that lacks in usefulness for R& D and for yield improvement. To mitigate the issue and to reduce yield improvement cycle in advanced technology, a novel method has been proposed. Instead of using random sampling method, we have applied a pattern search engine to correlate defect of interest (DOI) to its pattern background. Based on the approach we have identified an important defect type, STI cave defect, to be the major defect type on defect Pareto. For the defect type, stack die map was generated that indicated a distinctive signature. The result was compared against design layout to confirm that the defects were occurring at certain locations of design layout. Afterwards the defect types were reviewed using SEM and in-line FIB for further confirmation. We have found the cause of this void defect type to be poor gap-fill in deposition step. Based on the novel technique, we were able to filter out a systematic defect type quickly and efficiently from wafer map that consist of random and systematic defects.

Improving tool efficiency through automated process window qualification

It is widely understood that a close attention to systematic defect issue is required to succeed in a device development and production of 45 nm and beyond. For 45 nm, use of OPC created tremendous challenges in both optimization and validation of proper amount of optical correction needed1. OPC treatment and variation across wafer have to be controlled and monitored with utmost care where there can be issues near the edge of wafer or under process variations. Generally for 32 nm and beyond, Semiconductor industrys adoption of Immersion and Double Patterning Lithography (DPL) are bringing new challenges in controlling process for best yield. DPL sites can introduce patterning and overlay issues. To introduce a new process or device, Lithography process window must be well understood for faster process development and to prevent catastrophic yield loss. CD and overlay variations must be measured at the most appropriate sites across die and wafer to fully characterize a process. Today Lithography engineers are utilizing various approaches in understanding the process window including CD metrology and Defect inspection using wafers where Focus and Exposure conditions are modulated. Layout and ranges of conditions may vary based on devices and technology. Generally CD metrology provides good sensitivity to the process variation but it is often limited by ability to sample across wafer. Defect inspection provides much wider coverage but requires engineering resources for separating real pattern failure from particles or other pattern noise. In the past Litho process window qualification has been performed requiring much of manual intervention by users. In this paper, we introduce a new technique that enables automatic process window qualification that reduces user intervention while making the procedure repeatable among different users.

Systematic Defect Management by Design Aware Inspection

As electronic users demand smaller form factor of devices that can pack more functionality, Semiconductor industry has been marching towards smaller design rules. With the advancement in newer design nodes such as 32nm and beyond, additional challenges are being faced by the Fabs developing the process technologies. These challenges are often difficult to solve using traditional approaches and therefore novel techniques must be implemented to address the challenges accordingly. In the area of wafer inspection, the traditional approach of simply using wafer level data alone is no longer sufficient. Some specific challenges regarding systematic defects that the Fabs are facing today are discussed in this paper along with several approaches that can help meet the challenges. These new approaches can help to take the wafer inspection to the next level in order to detect and identify key yield deterrents that limit reaching yield entitlement in a timely manner.

Effective learning and feedback to designers through design and wafer inspection integration

As design rules continue to shrink beyond the lithography wavelength, pattern printability becomes a significant challenge in fabrication for 45nm and beyond. Model-based OPC and DRC checkers have been deployed using metrology data such as CD to fine-tune the model, and to predict and identify potential structures that may fail in a manufacturing environment. For advanced technology nodes with tighter process windows, it is increasingly important to validate the models with empirical data from both product and FEM wafers instead of relying solely on traditional metrology and simulations. Furthermore, feeding the information back to designers can significantly reduce the development efforts.