Ellis Chang

Using design based binning to improve defect excursion control for 45nm production

For advanced device (45 nm and below), we proposed a novel method to monitor systematic and random excursion. By integrating design information and defect inspection results into automated software (DBB), we can identify design/process marginality sites with defect inspection tool. In this study, we applied supervised binning function (DBC) and defect criticality index (DCI) to identify systematic and random excursion problems on 45 nm SRAM wafers. With established SPC charts, we will be able to detect future excursion problem in manufacturing line early.

Defect criticality index (DCI): a new methodology to significantly improve DOI sampling rate in a 45nm production environment

Increasing inspection sensitivity may be necessary for capturing the smaller defects of interest (DOI) dictated by reduced minimum design features. Unfortunately, higher inspection sensitivity can result in a greater percentage of non-DOI or nuisance defect types during inline monitoring in a mass production environment. Due to the time and effort required, review sampling is usually limited to 50 to 100 defects per wafer. Determining how to select and identify critical defect types under very low sampling rate conditions, so that more yield-relevant defect Paretos can be created after SEM review, has become very important. By associating GDS clip (design layout) information with every defect, and including defect attributes such as size and brightness, a new methodology called Defect Criticality Index (DCI) has demonstrated improved DOI sampling rates.

Improving tool efficiency through automated process window qualification

It is widely understood that a close attention to systematic defect issue is required to succeed in a device development and production of 45 nm and beyond. For 45 nm, use of OPC created tremendous challenges in both optimization and validation of proper amount of optical correction needed1. OPC treatment and variation across wafer have to be controlled and monitored with utmost care where there can be issues near the edge of wafer or under process variations. Generally for 32 nm and beyond, Semiconductor industrys adoption of Immersion and Double Patterning Lithography (DPL) are bringing new challenges in controlling process for best yield. DPL sites can introduce patterning and overlay issues. To introduce a new process or device, Lithography process window must be well understood for faster process development and to prevent catastrophic yield loss. CD and overlay variations must be measured at the most appropriate sites across die and wafer to fully characterize a process. Today Lithography engineers are utilizing various approaches in understanding the process window including CD metrology and Defect inspection using wafers where Focus and Exposure conditions are modulated. Layout and ranges of conditions may vary based on devices and technology. Generally CD metrology provides good sensitivity to the process variation but it is often limited by ability to sample across wafer. Defect inspection provides much wider coverage but requires engineering resources for separating real pattern failure from particles or other pattern noise. In the past Litho process window qualification has been performed requiring much of manual intervention by users. In this paper, we introduce a new technique that enables automatic process window qualification that reduces user intervention while making the procedure repeatable among different users.

Systematic Defect Management by Design Aware Inspection

As electronic users demand smaller form factor of devices that can pack more functionality, Semiconductor industry has been marching towards smaller design rules. With the advancement in newer design nodes such as 32nm and beyond, additional challenges are being faced by the Fabs developing the process technologies. These challenges are often difficult to solve using traditional approaches and therefore novel techniques must be implemented to address the challenges accordingly. In the area of wafer inspection, the traditional approach of simply using wafer level data alone is no longer sufficient. Some specific challenges regarding systematic defects that the Fabs are facing today are discussed in this paper along with several approaches that can help meet the challenges. These new approaches can help to take the wafer inspection to the next level in order to detect and identify key yield deterrents that limit reaching yield entitlement in a timely manner.

Accelerating 32nm BEOL technology development by advanced wafer inspection methodology

In the early development stage of 32nm processes, identifying and isolating systematic defects is critical to understanding the issues related to design and process interactions. Conventional inspection methodologies using random review sampling on large defect populations do not provide the information required to take accurate and quick corrective action. This paper demonstrates the successful identification and isolation of systematic defects using a novel methodology that combines Design Based Binning (DBB) and inline Defect Organizer (iDO). This new method of integrating design and defect data produced actionable inspection data, resulting in fewer mask revisions and reduced device development time.

Advanced method to monitor design-process marginality for 65nm node and beyond

We proposed a novel method (DBB: Designed Based Binning) by using design and defect inspection information to detect marginal design features. This method was used to identify a pattern failure problem (hammer head) which occurred during production early ramp (65 nm device). The traditional approach could not detect this hammerhead problem due to the intermittent nature and low defect count. This problem was identified by DBB methodology which showed problem root cause as a combination of lithography process conditions drift and marginal OPC issues. This use case proved that by using DBB to identify weak pattern features, it provides a common platform for designer, OPC and process engineer to communicate and identify design related problems faster. This method has helped integration engineer shorten process development time, supported product engineer to ramp new product faster and enabled defect engineer to detect excursion earlier. Overall, advanced manufacturing fab will achieve higher yield by adopting this.

Effective learning and feedback to designers through design and wafer inspection integration

As design rules continue to shrink beyond the lithography wavelength, pattern printability becomes a significant challenge in fabrication for 45nm and beyond. Model-based OPC and DRC checkers have been deployed using metrology data such as CD to fine-tune the model, and to predict and identify potential structures that may fail in a manufacturing environment. For advanced technology nodes with tighter process windows, it is increasingly important to validate the models with empirical data from both product and FEM wafers instead of relying solely on traditional metrology and simulations. Furthermore, feeding the information back to designers can significantly reduce the development efforts.

A holistic methodology to address leading edge FPGA manufacturing challenge

A yield ramp methodology for Field-Programmable Gate Array (FPGA) in advanced technologies has been presented. By optimizing design based defect inspection setups, we can use defect-to-bit overlay mapping method more effectively and more reliably in product failure debug [1]. This is complimentary to the manufacturing fabs test vehicles, electrical tests and physical failure analysis for faster wafer failure root cause analysis. With integrating the critical area analysis and defect criticality calculation, this proven methodology provides fab-less and fab-lit companies more tools in their efforts of design for yield, design for manufacturing and design for tests.