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Dive into the research topics where Alok Kumar Lohia is active.

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Featured researches published by Alok Kumar Lohia.


Journal of Electronic Packaging | 2010

Reliability Modeling of Lead-Free Solder Joints in Wafer-Level Chip Scale Packages

Jie-Hua Zhao; Vikas Gupta; Alok Kumar Lohia; Darvin R. Edwards

Board-level thermomechanical fatigue lifetimes of five different wafer-level chip scale packages (WCSPs) with lead-free solder joints were studied by both experiment and finite element method modeling. The effect of three different constitutive laws of the lead-free solder, namely Anand viscoplasticity, power law break-down creep, and time-hardening creep are also investigated for each of the five packages. The fatigue correlation parameters based on the increment of volume-averaged inelastic strain energy density are deduced for each of the corresponding three constitutive laws. It is demonstrated that the relative error of the predicted lifetime for WCSP with lead-free solder joints can be within 10% compared with experiment. It is found that the fatigue correlation parameters depend strongly on the specific constitutive law. Another important finding is that the fatigue correlation parameters depend on the specific package family. It is also demonstrated that when fatigue correlation parameters calibrated for other package families are applied to WCSPs, the error in predicted lifetimes is consistently large.


ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference | 2007

Reliability Modeling of Lead Free Solder Joints in Wafer-Level Chip Scale Packages

Jie-Hua Zhao; Vikas Gupta; Alok Kumar Lohia; Darvin R. Edwards

Board level thermomechanical fatigue lifetimes of five different wafer-level chip scale packages (WCSP’s) with lead-free solder joints were studied by both experiment and finite element method modeling. The effect of three different constitutive laws of the lead-free solder, namely Anand viscoplasticity, power law break-down creep and time hardening creep are also investigated for each of the five packages. The fatigue correlation parameters based on the increment of volume-averaged inelastic strain energy density are deduced for each of the corresponding three constitutive laws. It is demonstrated that the relative error of the predicted lifetime for WCSP with lead-free solder joints can be within 10% compared to experiment. It is found that the fatigue correlation parameters depend strongly on the specific constitutive law. Another important finding is that the fatigue correlation parameters depend on the specific package family. It is also demonstrated that when fatigue correlation parameters calibrated for other package families are applied to WCSPs, the error in predicted lifetimes is consistently large.Copyright


Archive | 2015

Structure and method of packaged semiconductor devices with bent-lead qfn leadframes

Andy Quang Tran; Reynaldo Corpuz Javier; Alok Kumar Lohia


Archive | 2007

Packaged integrated circuits and methods to form a stacked integrated circuit package

Reynaldo Corpuz Javier; Jayprakash V. Chipalkatti; Alok Kumar Lohia


Archive | 2016

FLAT NO-LEAD PACKAGES WITH ELECTROPLATED EDGES

Reynaldo Corpuz Javier; Alok Kumar Lohia; Andy Quang Tran


Archive | 2014

PACKAGED SEMICONDUCTOR DEVICES HAVING SOLDERABLE LEAD SURFACES EXPOSED BY GROOVES IN PACKAGE COMPOUND

Alok Kumar Lohia; Reynaldo Corpuz Javier; Andy Quang Tran


Archive | 2016

PACKAGED SEMICONDUCTOR DEVICE HAVING STACKED ATTACHED CHIPS OVERHANGING THE ASSEMBLY PAD

Alok Kumar Lohia; Reynaldo Corpuz Javier; Andy Quang Tran


Archive | 2015

Exposed pad integrated circuit package

Reynaldo Corpuz Javier; Alok Kumar Lohia; Andy Quang Tran


Archive | 2015

Structure and method of packaged semiconductor devices

Andy Quang Tran; Reynaldo Corpuz Javier; Alok Kumar Lohia


Archive | 2015

SEMI-HERMETIC SEMICONDUCTOR PACKAGE

Andy Quang Tran; Alok Kumar Lohia; Reynaldo Corpuz Javier

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