Amador Pérez-Tomás

A Survey of Wide Bandgap Power Semiconductor Devices

Wide bandgap semiconductors show superior material properties enabling potential power device operation at higher temperatures, voltages, and switching speeds than current Si technology. As a result, a new generation of power devices is being developed for power converter applications in which traditional Si power devices show limited operation. The use of these new power semiconductor devices will allow both an important improvement in the performance of existing power converters and the development of new power converters, accounting for an increase in the efficiency of the electric energy transformations and a more rational use of the electric energy. At present, SiC and GaN are the more promising semiconductor materials for these new power devices as a consequence of their outstanding properties, commercial availability of starting material, and maturity of their technological processes. This paper presents a review of recent progresses in the development of SiC- and GaN-based power semiconductor devices together with an overall view of the state of the art of this new device generation.

Inhibiting the absorber/Mo-back contact decomposition reaction in Cu2ZnSnSe4 solar cells: the role of a ZnO intermediate nanolayer

This work reports a process based on the use of an ultrathin (10 nm) ZnO intermediate layer for the improvement of the absorber/back contact interface region in Cu2ZnSnSe4 (CZTSe) kesterite solar cells. Raman microprobe measurements performed directly on the substrate surface after mechanical removal of the absorber layer indicate the occurrence of a decomposition reaction of Cu2ZnSnSe4 in contact with the Mo substrate. This leads to a significant degradation of the quality of the absorber/back contact interface, with the formation of a high density of voids. The presence of an intermediate ZnO layer on the Mo coated substrates inhibits the decomposition reaction, because it prevents interaction between the CZTSe and Mo layers during the annealing process. This leads to a significant improvement in the interface morphology as observed by detailed cross-section scanning electron microscopy. It also correlates with the observed increase of the device conversion efficiency from 2.5% up to 6.0%. The improvement in the optoelectronic characteristics of the cells could be related to a significant decrease of the device series resistance due to the formation of a smoother interface with low density of voids, resulting from the effective inhibition of the CZTSe decomposition reaction at the Mo back contact layer.

Field-effect mobility temperature modeling of 4H-SiC metal-oxide-semiconductor transistors

Here a physically based channel mobility model has been developed to investigate the temperature dependence of the field-effect mobility of 4H-SiC metal-oxide-semiconductor (MOS) transistors with thermally oxidized gate insulators. This model has been designed so that it accounts for the high density of traps at the MOS interface. This temperature dependence is a key issue for silicon carbide electronics, as its basic material properties make it the foremost semiconductor for high power/high temperature electronic devices in applications such as spacecraft, aircraft, automobile, and energy distribution. Our modeling suggests that the high density of charged acceptor interface traps, encountered in thermally grown gate oxides, modulates the channel mobility due to the Coulomb scattering of free carriers in the inversion layer. When the temperature increases, the field-effect mobility of these devices also increases, due to an increase in inversion charge and a reduction of the trapped charge. Experimental ...

Analysis of the AlGaN/GaN vertical bulk current on Si, sapphire, and free-standing GaN substrates

The vertical bulk (drain-bulk) current (Idb) properties of analogous AlGaN/GaN hetero-structures molecular beam epitaxially grown on silicon, sapphire, and free-standing GaN (FS-GaN) have been evaluated in this paper. The experimental Idb (25–300 °C) have been well reproduced with physical models based on a combination of Poole-Frenkel (trap assisted) and hopping (resistive) conduction mechanisms. The thermal activation energies (Ea), the (soft or destructive) vertical breakdown voltage (VB), and the effect of inverting the drain-bulk polarity have also been comparatively investigated. GaN-on-FS-GaN appears to adhere to the resistive mechanism (Ea = 0.35 eV at T = 25–300 °C; VB = 840 V), GaN-on-sapphire follows the trap assisted mechanism (Ea = 2.5 eV at T > 265 °C; VB > 1100 V), and the GaN-on-Si is well reproduced with a combination of the two mechanisms (Ea = 0.35 eV at T > 150 °C; VB = 420 V). Finally, the relationship between the vertical bulk current and the lateral AlGaN/GaN transistor leakage curr...

GaN transistor characteristics at elevated temperatures

The characteristics of different GaN transistor devices characterized at elevated temperatures for power applications are compared in this paper. High temperature characteristics of GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) and GaN high electron mobility transistors (HEMTs) are reported. For MOSFETs, the transconductance current (gm) increases with temperature, while for HEMTs is reduced. Their specific on resistance (Ron) follows the same trend. Specific contact resistivity (ρc) to implanted Si N+ GaN also diminishes with T, whereas for AlGaN/GaN ρc remains practically constant. We bring a more physical insight into the temperature behavior of these GaN devices by means of physics-based modeling in Sec. VI of this paper. The MOSFET’s field-effect mobility increases with T due to interface trap Coulomb scattering. Analogously, the HEMT’s gm decrease with T is attributed to a significant reduction in the two-dimensional electron gas carrier mobility due to polar-optical-phonon scatte...

Characterization and modeling of n-n Si/SiC heterojunction diodes

In this paper we investigate the physical and electrical properties of silicon layers grown by molecular beam epitaxy on 4H-SiC substrates, evaluating the effect of the Si doping, Si temperature deposition, and SiC surface cleaning procedure. Si∕SiC monolithic integration of Si circuits with SiC power devices can be considered as an attractive proposition and has the potential to be applied to a broad range of applications. X-ray diffraction and scanning electron microscopy are used to determine the Si crystal structure (cubic silicon) and morphology. I-V and C-V measurements are performed to evaluate the rectifying diode characteristics along with the Si∕SiC built-in potential and energy band offsets. In the last section, we propose that our Si∕SiC heteojunction diode current characteristics can be explained by an isojunction drift-diffusion and thermoionic emission model where the effect of doping concentration of the silicon layer and its conduction band offset with SiC is analyzed.

Modelling the inhomogeneous SiC Schottky interface

For the first time, the I-V-T dataset of a Schottky diode has been accurately modelled, parameterised, and fully fit, incorporating the effects of interface inhomogeneity, patch pinch-off and resistance, and ideality factors that are both heavily temperature and voltage dependent. A Ni/SiC Schottky diode is characterised at 2 K intervals from 20 to 320 K, which, at room temperature, displays low ideality factors (n   8), voltage dependent ideality factors and evidence of the so-called “thermionic field emission effect” within a T0-plot, suggest significant inhomogeneity. Two models are used, each derived from Tungs original interactive parallel conduction treatment of barrier height inhomogeneity that can reproduce these commonly seen effects in single temperature I-V traces. The first model incorporates patch pinch-off effects and produces accurate and reliable fits above around 150 K, and at current densities lower than 10−5 A cm−2. Outside this region, we show that resistive effects within a given patch are responsible for the excessive ideality factors, and a second simplified model incorporating these resistive effects as well as pinch-off accurately reproduces the entire temperature range. Analysis of these fitting parameters reduces confidence in those fits above 230 K, and questions are raised about the physical interpretation of the fitting parameters. Despite this, both methods used are shown to be useful tools for accurately reproducing I-V-T data over a large temperature range.

Micro and nano analysis of 0.2 Ω mm Ti/Al/Ni/Au ohmic contact to AlGaN/GaN

As GaN technology continues to gain popularity, it is necessary to control the ohmic contact properties and to improve device consistency across the whole wafer. In this paper, we use a range of submicron characterization tools to understand the conduction mechanisms through the AlGaN/GaN ohmic contact. Our results suggest that there is a direct path for electron flow between the two dimensional electron gas and the contact pad. The estimated area of these highly conductive pillars is around 5% of the total contact area.

Characterization of High-k Ta2Si Oxidized Films on 4H-SiC and Si Substrates as Gate Insulator

The main physical and electrical characteristics of the high-k insulator layer produced by the Ta 2 Si deposition and subsequent oxidation on SiC and Si substrates are investigated in this paper. The leakage current of these layers shows an asymmetric behavior with the polarity of the gate bias (gate +V or -V), yielding a leakage current density as low as 10 - 8 A cm - 2 at I MV cm - 1 and 4.5 MV cm - 1 , respectively. To identify the conduction mechanisms, the experimental current-voltage curves have been fitted with a theoretical model accounting for a double hopping and tunnel/Poole-Frenkel conduction mechanism. The dielectric constant obtained for a 4H-SiC metal-insulator semiconductor (MIS) is ∼20 basically independent of the insulator thickness or the oxidation temperature. The dielectric constant obtained for Si MIS capacitors decreases with increasing oxidation temperature, and its value has been measured in the 10-7 range. 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) have been fabricated using oxidized Ta 2 Si as a gate insulator, demonstrating the feasibility of this insulator and reporting one of the first well-behaved MOSFETs on SiC with high-k gate dielectric. For the MOSFETs fabricated on a p-implanted and annealed region, a peak mobility up to 40 cm 2 /Vs has been extracted, which is higher than mobilities commonly reported for thermal oxidized 4H-SiC MOSFETs.

High doped MBE Si p-n and n-n heterojunction diodes on 4H-SiC

The physical and electrical properties of heavily doped silicon (5x10^1^9cm^-^3) deposited by molecular beam epitaxy (MBE) on 4H-SiC are investigated in this paper. Silicon layers on silicon carbide have a broad number of potential applications including device fabrication or passivation when oxidised. In particular, Si/SiC contacts present several atractive material advantages for the semiconductor industry and especially for SiC processing procedures for avoiding stages such as high temperature contact annealing or SiC etching. Si films of 100nm thickness have been grown using a MBE system after different cleaning procedures on n-type (0001) Si face 8^o off 4H-SiC substrates. Isotype (n-n) and an-isotype (p-n) devices were fabricated at both 500 and 900^oC using antimonium (Sb) or boron (B), respectively. X-ray diffraction analysis (XRD) and scanning electronic mircorscope (SEM) have been used to investigate the crystal composition and morphology of the deposited layers. The electrical mesurements were performed to determine the rectifiying contact characteristics and band offsets.