Aman Gayasen

Reducing leakage energy in FPGAs using region-constrained placement

FPGAs are being increasingly used in a wide variety of applications. While power optimization has been only of secondary importance in many FPGA applications, growing importance of leakage in FPGAs designed in 90nm and below makes it imperative to treat power optimization as a first class citizen. In this paper, we propose a leakage-saving technique for FPGAs that involves dividing the FPGA fabric into small regions and switching on/off the power supply to each region using a sleep transistor in order to conserve leakage energy. Specifically, the regions not used by the placed design are supply gated. Next, we present a new placement strategy to increase the number of regions that can be supply gated. Finally, the supply gating technique is extended to exploit idleness in different parts of the same design during different time periods. Our experiments with different region sizes using various commercial and academic designs indicate that the proposed optimization outperforms conventional placement, and reduces leakage power consumption significantly.

A Dual-VDD Low Power FPGA Architecture

The continuing increase in FPGA size and complexity and the emergence of sub-100nm technology have made FPGA power consumption, both dynamic and static, an important design consideration. In this work, we propose a programmable dual-V DD architecture in which the supply voltage of the logic blocks and routing blocks are programmed to reduce power consumption by assigning low-V DD to non-critical paths in the design, while assigning high-V DD to the timing critical paths in the design to meet timing constraints. We evaluate the effectiveness of different V DD assignment algorithms and architectural implementations. Our experimental results show that reducing the supply voltage selectively to the non-critical paths provides significant power savings with minimal impact on performance. One of our V DD -assignment techniques provides an average power saving of 61% across different MCNC benchmarks.

Improving soft-error tolerance of FPGA configuration bits

Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it important to increase their immunity to soft errors. In this work, we propose the use of an asymmetric SRAM (ASRAM) structure that is optimized for soft error immunity and leakage when storing a preferred value. The key to our approach is the observation that the configuration bitstream is composed of 87% of zeros across different designs. Consequently, the use of ASRAM cell optimized for storing a zero (ASRAM-0) reduces the failure in time by 25% as compared to the original design. We also present an optimization that increases the number of zeros in the bitstream while preserving the functionality.

Exploring technology alternatives for nano-scale FPGA interconnects

Field programmable gate arrays (FPGAs) are becoming increasingly popular. With their regular structures, they are particularly amenable to scaling to smaller technologies. On the other hand, there have been significant advances in nano-electronics fabrication over the past few years. In this paper we explore FPGA devices of the next decade using nano-wires and molecular switches for programmable interconnect, and compare them to traditional SRAM-based FPGAs that use pass transistors as switches (scaled to 22nm). We show that by using nano-wires and molecular switches, it is possible to reduce the area of the FPGA by 70% and improve performance.

A Hardware Efficient Support Vector Machine Architecture for FPGA

In real-time video mining applications it is desirable to extract information about human subjects, such as gender, ethnicity, and age, from grayscale frontal face images. Many algorithms have been developed in the machine learning, statistical data mining, and pattern classification communities that perform such tasks with remarkable accuracy. Many of these algorithms, however, when implemented in software, suffer poor frame rates due to the amount and complexity of the computation involved. This paper presents an FPGA friendly implementation of a Gaussian Radial Basis SVM well suited to classification of grayscale images. We identify a novel optimization of the SVM formulation that dramatically reduces the computational inefficiency of the algorithm. The implementation achieves 88.6% detection accuracy in gender classification which is to the same degree of accuracy of software implementations using the same classification mechanism.

Leakage control in FPGA routing fabric

As FPGA designs in 65nm are being explored, reducing leakage power becomes an important design issue. A significant portion of the FPGA leakage is expended in the unused multiplexers used in the interconnect fabric. This work focuses on reducing the leakage of these unused multiplexers by controlling their inputs. We investigate the design issues involved in implementing such a technique and also show experimental results demonstrating the effectiveness of our approach.

Thermal characterization and optimization in platform FPGAs

Increasing power densities in field programmable gate arrays (FPGAs) have made them susceptible to thermal problems. The advent of platform FPGAs has further exacerbated the problems by increasing the power density variations on the FPGA fabric. Therefore, we need to characterize the die temperature of platform FPGAs. In this paper, we first estimate the temperature distribution within a Virtex-4 FPGA by feeding the block power numbers in an architecture-level temperature simulator calibrated to reflect a real FPGA package. We analyze the impact of different hard-wired blocks on the temperature profile, and observe that they introduce intra-die variation in temperature of up to 20degC. Next, we evaluate the influence of placement on temperature. Our experiments indicate a decrease in peak temperature by changing the placement of hard blocks, especially the high-speed transceivers. We further propose an iterative placement technique to reduce the peak temperature, and apply it on real designs. Finally, we propose alternate organizations of the hard blocks in the FPGA fabric to reduce temperature

Improving Java performance using dynamic method migration on FPGAs

With the diffusion of Java in advanced multimedia mobile devices, there is a growing need for speeding up the execution of Java bytecode beyond the limits of traditional interpreters and just-in-time compilers. In this area, Java coprocessors are viewed as a promising technology, which marries the flexibility of a general-purpose microprocessor to run legacy code and lightweight Java methods, with the high performance of a specialised execution engine on speed-critical bytecode. This work proposes and analyses a microprocessor with FPGA coprocessor architecture with efficient shared-memory communication support. Furthermore, we describe a complete run-time environment that supports dynamic migration of Java methods to the coprocessor, and we quantitatively analyse speedups achievable under a number of system configurations using an accurate complete-system simulator.

Switch Box Architectures for Three-Dimensional FPGAs

In this paper, the authors explore six 3D switch box (SB) topologies for the case when the vias are fewer than the horizontal wires. Using detailed area and delay models, we estimate their impact on FPGA area, delay, and area-delay product. The results indicate that the area-delay product (ADP) depends heavily on the SB topology: our best SB reduces ADP by 9% compared to the subset SB

Leveraging Emerging Technology Through Architectural Exploration for the Routing Fabric of Future FPGAs

Field-programmable gate arrays (FPGAs) have become very popular in recent times. With their regular structures, they are particularly amenable to scaling to smaller technologies. They form an excellent platform for studying emerging technologies. Recently, there have been significant advances in nanoelectronics fabrication that make them a viable alternative to CMOS. One such promising alternative is bundles of single-walled carbon nanotube (SWCNT).