Amin Farshidi

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes

Minimizing power and skew for clock networks are critical and difficult tasks which can be greatly affected by buffer sizing. However, buffer sizing is a non-linear problem and most existing algorithms are heuristics that fail to obtain a global minimum. In addition, existing buffer sizing solutions do not usually consider manufacturing variations. Any design made without considering variation can fail to meet design constraints after manufacturing. In this paper, first we proposed an efficient optimization scheme based on geometric programming (GP) for buffer sizing of clock networks. Then, we extended the GP formulation to consider process variations in the buffer sizes using robust optimization (RO). The resultant variation-aware network is examined with SPICE and shown to be superior in terms of robustness to variations while decreasing area, power and average skew.

A pre-placement individual net length estimation model and an application for modern circuits

With the advances in integrated circuit (IC) technology, managing the individual and total interconnect is becoming one of the main challenges facing designers. An individual a-priori length estimation model can be a useful tool in helping designers obtain lower net lengths and congestion of interconnect. In this paper, the main characteristics that need to be considered while designing an individual a-priori length estimation technique for todays integrated circuits are discussed. A model that includes some of the most prevalent characteristics is designed and tested using the most current benchmark circuits released by IBM. In addition, one application of the length estimation is proposed in which a predictor-corrector framework for clustering that can be used to improve the results of placement is implemented. This model shows that the corrector step can improve the final placement results by up to 33% for special cases.

A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications

Most engineering problems involve optimizing different and competing objectives. To solve multi-objective problems, normally a weighted sum of the objectives is optimized. However, how the weights are assigned can greatly affect the outcome. Therefore, many designers have to resort to producing the Pareto surface - a time-consuming procedure. In this paper, we propose a framework for solving multi-objective geometric programming problems where weights in the objective are optimally calculated during the optimization problem without having to produce the Pareto surface. It is shown that the proposed self-tuning multi-objective framework can be applied to geometric programming gate sizing problems. Then, the efficacy of the proposed framework is proven using the clock network buffer sizing problem as an application. The problem is first formulated as a geometric programming (GP) problem with the objectives of reducing power, skew, and slew. The problem is solved using ISPD09 circuits. The power, skew and slew of the optimized networks are calculated using ngspice. The results show on average 52% reduction in power and 28% reduction in skew compared to the original networks. The self-tuning multi-objective solution is shown superior to any single objective solution with no impact on runtime.

A new a priori net length estimation technique for integrated circuits using radial basis functions

Abstract Placement is a stage in the design of digital circuits where the locations of the circuit components are determined, while minimizing the total length of wires connecting them. A priori individual length estimates can be used to improve the quality of a placement solution. However, finding such estimates is a daunting task. A technique based on Radial Basis Functions (RBFs) is developed in this paper. Unlike polynomials, the RBFs provide flexible basis elements with only local support, which greatly enhances both their robustness and their ability to fit highly non-linear data sets. Today’s placement problems deal with a very large number of components making it impossible to apply traditional RBF modeling techniques. Thus specialized methods for determining the RBF centers and shape parameters are developed. The proposed technique is tested on popular benchmark circuits, and shows improvements of up to 24% over the best existing model for mixed-size circuits.

Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem

In this paper, we present and analyze four efficient models that produce significantly improved results by optimizing conflicting power and skew objectives in the clock network buffer sizing problem. Each model is in geometric programming format and has certain advantages, such as maximum reduction in power, robustness to process variation, and striking a balance between skew and power optimization. The buffer sizing problem is formulated as a geometric programming problem to provide globally optimal solutions to the four models. We also show that a geometric programming multiobjective model can be used to optimize both power and skew without requiring any tuning from a designer. The presented self-tuning multiobjective formulation not only provides optimal solutions for buffer sizes, but also finds the tuning parameters that result in overall combined reduction in power and skew without loss of convexity. The effectiveness of the models are illustrated on several publicly available benchmarks. The models provide on average 40% to 60% improvement in power while reducing skew in several cases. We have also proposed a smart heuristic for discretization of the continuous geometric programming solution that preserves skew and power. Finally, we provide a guideline for designers to decide which one of the proposed models is the most appropriate for their needs.

A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees

Clock buffer and wire sizing are intertwined problems that also greatly impact power consumption and skew in clock trees. Due to their complexity, they are often solved separately, leading to suboptimal solutions. In this brief, we propose a new formulation for cooptimization of buffer and wire sizes for high-performance clock trees. Using the proposed cooptimization of buffer and wire sizes, we are able to minimize a combination of both power and skew. The variation-aware experiments show that, by applying the proposed formulation, power and skew for all tested clock trees are improved. On average, we achieve a reduction of 57% in power and 50 ps in skew. We also show that our solutions are Pareto optimal where power and skew cannot be further reduced simultaneously and they provide a balanced tradeoff between power and skew.

A new length-based algebraic multigrid clustering algorithm

Clustering algorithms have been used to improve the speed and quality of placement. Traditionally, clustering focuses on the local connections between cells. In this paper, a new clustering algorithm that is based on the estimated lengths of circuit interconnects and the connectivity is proposed. In the proposed algorithm, first an a priori length estimation technique is used to estimate the lengths of nets. Then, the estimated lengths are used in a clustering framework to modify a clustering technique based on algebraic multigrid (AMG), that finds the cells with the highest connectivity. Finally, based on the results from the AMG-based process, clusters are made. In addition, a new physical unclustering technique is proposed. The results show a significant improvement, reductions of up to 40%, in wire length can be achieved when using the proposed technique with three academic placers on industry-based circuits. Moreover, the runtime is not significantly degraded and can even be improved.

The impact of industry-organized contests on EDA education

The Electronic Design Automation (EDA) community is faced with an exponential increase in the complexity of the problems that it has to solve. These problems challenge the EDA community to find innovative techniques for training the next generation of researchers. This work discuss how international contests in EDA can play a pivotal role in the education and industry practices. We discuss the impact of our these contests on bridging the gap between industry and academia, training of the graduate students and building collaborations between different researchers. We compare the impact of papers originated from the effort of team winners in such contests compared to the best papers in annual International Symposium on Physical Design (ISPD) conference and Design Automation Conference (DAC). Finally, we also discuss the impact of the contests on the industry organizers and how they benefit from them.

Sizing Digital Circuits Using Convex Optimization Techniques

This chapter collects recent advances in using convex optimization techniques to perform sizing of digital circuits. Convex optimization techniques provide an undeniably attractive promise: The attained solution is the best available. In order to use convex optimization techniques, the target optimization problem must be modeled using convex functions. The gate sizing problem has been modeled in different ways to enable the use of convex optimization techniques, such as linear programming and geometric programming. Statistical and robust sizing methods are included to reflect the importance of optimization techniques that are aware of variations. Applications of multi-objective optimization techniques that aid designers in evaluating the trade-offs are described.

Analysis of post-placement length estimation

Recently, there has been large emphasis on congestion based placement where the quality of placement is measured using the global routing results. However, as grid cells are used during global routing, only net segments that are mapped to the global routing grid are considered and no consideration is given to nets that are entirely or partially inside a grid cell and are eliminated during global routing. Hence, feasibility problems can arise during detailed routing where a seemingly good placement and global routing solution becomes infeasible when ignored net segments are visited. In this abstract, we propose a technique with linear time complexity which can give an accurate measure for the routing density of each grid cell and hence the entire circuit.