Logan Rakai

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes

Minimizing power and skew for clock networks are critical and difficult tasks which can be greatly affected by buffer sizing. However, buffer sizing is a non-linear problem and most existing algorithms are heuristics that fail to obtain a global minimum. In addition, existing buffer sizing solutions do not usually consider manufacturing variations. Any design made without considering variation can fail to meet design constraints after manufacturing. In this paper, first we proposed an efficient optimization scheme based on geometric programming (GP) for buffer sizing of clock networks. Then, we extended the GP formulation to consider process variations in the buffer sizes using robust optimization (RO). The resultant variation-aware network is examined with SPICE and shown to be superior in terms of robustness to variations while decreasing area, power and average skew.

A pre-placement net length estimation technique for mixed-size circuits

An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimation technique for mixed-size circuits is proposed. The proposed technique is capable of predicting the wire lengths for individual nets, and uses both relevant factors used in previous research as well as new factors that can affect the net lengths in mixed-size designs. The proposed models main characteristics include reporting individual net lengths, suitability for mixed-size designs, and the power to predict pre-placement net lengths before and after clustering. The net lengths estimated by this model are shown to be an average of 10% more correlated to after placement lengths compared to the most elaborated model of literature. The model can be used for a priori individual net length estimation and predicting the possible effects of clustering on lengths of individual nets during the placement stage.

A pre-placement individual net length estimation model and an application for modern circuits

With the advances in integrated circuit (IC) technology, managing the individual and total interconnect is becoming one of the main challenges facing designers. An individual a-priori length estimation model can be a useful tool in helping designers obtain lower net lengths and congestion of interconnect. In this paper, the main characteristics that need to be considered while designing an individual a-priori length estimation technique for todays integrated circuits are discussed. A model that includes some of the most prevalent characteristics is designed and tested using the most current benchmark circuits released by IBM. In addition, one application of the length estimation is proposed in which a predictor-corrector framework for clustering that can be used to improve the results of placement is implemented. This model shows that the corrector step can improve the final placement results by up to 33% for special cases.

GPU-Accelerated Solutions to Optimal Power Flow Problems

The optimal power flow problem (OPF) has been of importance to power system operators for many decades. Being able to quickly determine optimal operating points and analyzing larger networks can lead to advantages for operators from reliability, stability, cost and market fairness perspectives. This work aims at achieving those ends by solving OPF problems by utilizing hardware acceleration capabilities of graphical processing units (GPUs). At present, nearly all desktop and laptop computers ship with general-purpose GPUs that can be harnessed to accelerate analysis. This work will present important concepts regarding effective use of GPUs as it pertains to OPF problems and illustrate the types of problems that stand to benefit most from their use. The benefits of GPU acceleration are demonstrated by implementing a predictor-corrector interior-point method with the majority of the computation offloaded onto a GPU. Experiments are used to validate the developments by analyzing well-known power systems.

A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications

Most engineering problems involve optimizing different and competing objectives. To solve multi-objective problems, normally a weighted sum of the objectives is optimized. However, how the weights are assigned can greatly affect the outcome. Therefore, many designers have to resort to producing the Pareto surface - a time-consuming procedure. In this paper, we propose a framework for solving multi-objective geometric programming problems where weights in the objective are optimally calculated during the optimization problem without having to produce the Pareto surface. It is shown that the proposed self-tuning multi-objective framework can be applied to geometric programming gate sizing problems. Then, the efficacy of the proposed framework is proven using the clock network buffer sizing problem as an application. The problem is first formulated as a geometric programming (GP) problem with the objectives of reducing power, skew, and slew. The problem is solved using ISPD09 circuits. The power, skew and slew of the optimized networks are calculated using ngspice. The results show on average 52% reduction in power and 28% reduction in skew compared to the original networks. The self-tuning multi-objective solution is shown superior to any single objective solution with no impact on runtime.

A new a priori net length estimation technique for integrated circuits using radial basis functions

Abstract Placement is a stage in the design of digital circuits where the locations of the circuit components are determined, while minimizing the total length of wires connecting them. A priori individual length estimates can be used to improve the quality of a placement solution. However, finding such estimates is a daunting task. A technique based on Radial Basis Functions (RBFs) is developed in this paper. Unlike polynomials, the RBFs provide flexible basis elements with only local support, which greatly enhances both their robustness and their ability to fit highly non-linear data sets. Today’s placement problems deal with a very large number of components making it impossible to apply traditional RBF modeling techniques. Thus specialized methods for determining the RBF centers and shape parameters are developed. The proposed technique is tested on popular benchmark circuits, and shows improvements of up to 24% over the best existing model for mixed-size circuits.

A Detailed Routing-Aware Detailed Placement Technique

In this paper we propose a detailed placement algorithm targeting detailed rout ability for designs at or smaller than 22nm. The sheer number and complexity of routing design rules at these feature sizes preclude direct incorporation of detailed routing rules into a placement algorithm. However, using the detail routing information to guide the placement can significantly reduce the overall design time and improve the performance of the circuit. Our proposed detailed routing-aware detailed placement (DrDp) is developed as an add-on to the detailed placement process to improve detailed rout ability in a relatively short runtime. The proposed technique is added to the code obtained from one of the top three teams in the ISPD 2014 detailed routing-driven placement contest and tested on ISPD 2014 benchmark suite. Numerical results show that the proposed technique can improve the detailed routing quality with no significant change in detailed placement score, total wire length or runtime.

Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem

In this paper, we present and analyze four efficient models that produce significantly improved results by optimizing conflicting power and skew objectives in the clock network buffer sizing problem. Each model is in geometric programming format and has certain advantages, such as maximum reduction in power, robustness to process variation, and striking a balance between skew and power optimization. The buffer sizing problem is formulated as a geometric programming problem to provide globally optimal solutions to the four models. We also show that a geometric programming multiobjective model can be used to optimize both power and skew without requiring any tuning from a designer. The presented self-tuning multiobjective formulation not only provides optimal solutions for buffer sizes, but also finds the tuning parameters that result in overall combined reduction in power and skew without loss of convexity. The effectiveness of the models are illustrated on several publicly available benchmarks. The models provide on average 40% to 60% improvement in power while reducing skew in several cases. We have also proposed a smart heuristic for discretization of the continuous geometric programming solution that preserves skew and power. Finally, we provide a guideline for designers to decide which one of the proposed models is the most appropriate for their needs.

Minimizing Deployment Cost of Cloud-Based Web Application with Guaranteed QoS

Cloud computing provides a reliable and cost- effective setting for deploying large-scale web applications. However, choosing and configuring an appropriate cloud Infrastructure-as-a-Service (IaaS), e.g., the appropriate database and computing instances and acceptable service rates, is a daunting task. The task is also challenging when trying to optimize the IaaS for conflicting objectives such as performance and cost. Furthermore, due to lack of understanding of the pricing model and the cloud IaaS, a cloud consumer may pay more than necessary or may not fully utilize the purchased resources. For this reason, we propose an algorithm that suggests the most cost-effective configuration meeting the QoS requirements and budget constraint. In contrast to existing cost optimization proposals, our proposed algorithm maps the minimum requirements of the to- be-deployed web application to deployment costs according to the price model set by cloud providers. The algorithm also considers QoS requirements for different resource types in the cloud, namely, database servers, computing servers, storage, and service rate. The proposed algorithm is evaluated by a series of experiments on a web application with seven different workload scenarios. The experimental results show the effectiveness of the proposed algorithm in achieving a solution with the minimum deployment cost for each scenario while satisfying all customers requirements.

An algebraic multigrid-based algorithm for circuit clustering

Abstract Digital circuits have grown exponentially in their sizes over the past decades. To be able to automate the design of these circuits, efficient algorithms are needed. One of the challenging stages of circuit design is the physical design where the physical locations of the components of a circuit are determined. Coarsening or clustering algorithms have become popular with physical designers due to their ability to reduce circuit sizes in the intermediate design steps such that the design can be performed faster and with higher quality. In this paper, a new clustering algorithm based on the algebraic multigrid (AMG) technique is presented. In the proposed algorithm, AMG is used to assign weights to connections between cells of a circuit and find cells that are best suited to become the initial cells for clusters, seed cells. The seed cells and the weights between them and the other cells are then used to cluster the cells of a circuit. The analysis of the proposed algorithm proves linear-time complexity, O ( N ), where N is the number of pins in a circuit. The numerical experiments demonstrate that AMG-based clustering can achieve high quality clusters and improve circuit placement designs with low computational cost.