Andrew A. Kennings

A semidefinite optimization approach for the single-row layout problem with unequal dimensions

The facility layout problem is concerned with the arrangement of a given number of rectangular facilities so as to minimize the total cost associated with the (known or projected) interactions between them. We consider the one-dimensional space-allocation problem (ODSAP), also known as the single-row facility layout problem, which consists in finding an optimal linear placement of facilities with varying dimensions on a straight line. We construct a semidefinite programming (SDP) relaxation providing a lower bound on the optimal value of the ODSAP. To the best of our knowledge, this is the first non-trivial global lower bound for the ODSAP in the published literature. This SDP approach implicitly takes into account the natural symmetry of the problem and, unlike other algorithms in the literature, does not require the use of any explicit symmetry-breaking constraints. Furthermore, the structure of the SDP relaxation suggests a simple heuristic procedure which extracts a feasible solution to the ODSAP from the optimal matrix solution to the SDP relaxation. Computational results show that this heuristic yields a solution which is consistently within a few percentage points of the global optimal solution.

Engineering details of a stable force-directed placer

Analytic placement methods that simultaneously minimize wire length and spread cells are receiving renewed attention from both academia and industry. We describe the implementation details of a force-directed placer, FDP. Specifically, we provide: (1) a description of efficient force computation for spreading cells; (2) an illustration of numerical instability in these methods and a means by which these instabilities are avoided; (3) spread metrics for measuring cell distribution throughout the placement region; and (4) a complementary technique which aids in directly minimizing HPWL. We present results comparing our analytic placer to other academic tools for both standard cell and mixed-size designs. Compared to Kraftwerk and Capo 8.7, our tool produces results with an average improvement of 9% and 3%, respectively.

Symmetric Multiprocessing on Programmable Chips Made Easy

Vendor-provided softcore processors often support advanced features such as caching that work well in uniprocessor or uncoupled multiprocessor architectures. However, it is a challenge to implement symmetric multiprocessor on a programmable chip (SMPoPC) systems using such processors. This paper presents an implementation of a tightly coupled, cache-coherent symmetric multiprocessing architecture using a vendor-provided softcore processor. Experimental results show that this implementation can be achieved without invasive changes to the vendor-provided softcore processor and without degradation of the performance of the memory system.

FPGA-Based Lossless Data Compression using Huffman and LZ77 Algorithms

Lossless data compression algorithms are widely used by data communication systems and data storage systems to reduce the amount of data transferred and stored. GZIP is a popular, patent-free compression program that delivers good compression ratios. This paper presents hardware implementations for the LZ77 encoders and Huffman encoders that form the basis for a full hardware implementation of a GZIP encoder. The designs have been implemented as state machines in VHDL in such a way that they are suitable for implementation using either FPGA or ASIC technologies. Performance metrics and resource utilization results obtained for a prototype implementation running on an Altera DE2 board are presented. Ultimately, the goal is to utilized the LZ77 encoders and Huffman encoders described in this paper to build a fully-functional, hardware design for a GZIP encoder that could be used in data communication systems and data storage systems to boost overall system performance.

Analytical minimization of half-perimeter wirelength

Global placement of hypergraphs is critical in the top-down placement of large timing-driven designs. Placement quality is evaluated in terms of the half-perimeter wirelength (HPWL) of hyperedges in the original circuit hypergraph provided timing constraints are met. Analytical placers are instrumental in handling non-linear timing models, but have two important drawbacks: (a) corresponding optimization algorithms are typically slower than top-down methods driven by multi-level mincut partitioning, and (b) hyperedges must be represented with net models which imply a mismatch of objective functions, with the alternative of computationally expensive linear programming (LP). By comparing to optimal solutions produced by linear programming, we show that net models lead to solution quality loss. To address this problem, we present the first analytical algorithm that does not require net models and permits a direct inclusion of non-linear delay terms; this allows to avoid expensive linearization of delay terms. Our numerical engine utilizes well-known quadratically convergent Newton-type methods for speed; it produces solutions within 12% of the LP optimum. Empirical results are for industrial placement instances.

Improving Timing-Driven FPGA Packing with Physical Information

The traditional approach to FPGA packing and CLB-level placement has been shown to yield significantly worse quality than approaches which allow BLEs to move during placement. In practice, however, modern FPGA architectures require expensive DRC checks which can render full BLE-level placement impractical. We address this problem by proposing a novel clustering framework that uses physical information to produce better initial packings which can, in turn, reduce the amount of BLE-level placement that is required. We quantify our packing technique across accepted benchmarks and show that it produces results with 16% less wire length, 19% smaller minimum channel widths, and 8% less critical path delay, on average, than leading methods.

Board-level multiterminal net assignment for the partial cross-bar architecture

This paper presents a satisfiability-based method for solving the board-level multiterminal net routing problem in the digital design of clos-folded field-programmable gate array (FPGA) based logic emulation systems. The approach transforms the FPGA board-level routing task into a Boolean equation. Any assignment of input variables that satisfies the equation specifies a valid routing. We use two of the fastest Boolean satisfiability (SAT) solvers: Chaff and DLMSAT to perform our experiments. Empirical results show that the method is time-efficient and applicable to large layout problem instances.

Force-Directed Methods for Generic Placement

This paper describes the implementation of a wire length-driven force-directed placer named FDP for generic placement. Specifically, it describes efficient force computation for cell spreading, numerical instabilities during force-directed placement, a means to avoid instabilities, and metrics for proper assessment of cell distribution throughout the placement region. It demonstrates that one of the greatest impediments to achieving high-quality placements using a force-directed placer lies in the large amount of cell overlap present in initial placements. This overlap makes the determination of cell ordering difficult and can lead to the inadvertent separation of highly connected cells. It is shown that median improvement and multilevel clustering improve cell ordering and aid in wire length minimization. Numerical results are presented for both standard cell and mixed-size placement problems. For standard cell problems, the tool generates placements that are, on average, 3% better than Capo9.0, but 5% worse than FengShui2.6. For mixed-size problems, FDP generated placements that are, on average, 2%-5% better than Capo9.0 and -5%--2% better than Fengshui2.6, depending on the presence (or absence) of pin offsets. Run times for FDP are higher than both Capo9.0 and FengShu2.6, although reasonable

Segmented channel routability via satisfiability

Segmented channel routing is fundamental to the routing of row-based FPGAs. In this paper, we study segmented channel routability via satisfiability. Our method encodes the horizontal and vertical constraints of the routing problem as Boolean conditions. The routability constraint is satisfiable if and only if the net connections in the segmented channel are routable. Empirical results show that the method is time-efficient and applicable to large problem instances.

Improving Simulated Annealing-Based FPGA Placement With Directed Moves

Simulated annealing remains a widely used heuristic for field-programmable gate array placement due, in part, to its ability to produce high-quality placements while accommodating complex objective functions. This paper discusses enhancements to annealing-based placement which improve upon both quality and run-time. Specifically, intelligent strategies for selecting and placing cells are interspersed with traditional random moves during an anneal, allowing the annealer to converge more quickly and to attain better quality with less statistical variability. For the same amount of computational effort, the contributions discussed in this paper consistently improve both critical path delay and wire length compared to traditional annealing perturbations.