Amir Charif

Assessing Contact Graph Routing Performance and Reliability in Distributed Satellite Constellations

Existing Internet protocols assume persistent end-to-end connectivity, which cannot be guaranteed in disruptive and high-latency space environments. To operate over these challenging networks, a store-carry-and-forward communication architecture called Delay/Disruption Tolerant Networking (DTN) has been proposed. This work provides the first examination of the performance and robustness of Contact Graph Routing (CGR) algorithm, the state-of-the-art routing scheme for space-based DTNs. To this end, after a thorough description of CGR, two appealing satellite constellations are proposed and evaluated by means of simulations. Indeed, the DtnSim simulator is introduced as another relevant contribution of this work. Results enabled the authors to identify existing CGR weaknesses and enhancement opportunities.

Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU

As the number of processing elements in modern chips keeps increasing, the evaluation of new designs will need to account for various challenges at the NoC level. To cope with the impractically long run times when simulating large NoCs, we introduce a novel GPU-based parallel simulation method that can speed up simulations by over 250×, while offering RTL-like accuracy. These promising results make our simulation method ideal for evaluating future NoCs comprising thousands of nodes.

Addressing transient routing errors in fault-tolerant Networks-on-Chips

NoCs (Networks-on-Chips) are being viewed as the paradigm of choice for on-chip communication in modern SoCs (Systems-on-chips). Unfortunately, continuous technology downscaling is rendering NoC components increasingly susceptible to failure, to a point where it is no longer an option to design such systems without accounting for reliability issues. In this work, we concern ourselves with faults affecting one of the most important logical units in NoC routers, namely the Route Computation Unit. To prevent deadlocks and packet loss, which may result from misrouting, we propose a solution to detect and correct route computation errors. With compatibility with non-minimal fault-tolerant adaptive routing algorithms in mind, two detection methods are proposed. Lazy detection only detects the faults that may result in an error immediately following route computation, and leaves it to the next hops to detect and correct other errors. Strict detection detects all fatal errors before the affected packets leave the faulty router, making it possible to correct all errors using a single rerouting mechanism. Finally, we propose a novel method to safely correct routing errors and deliver all packets to their destination without resorting to retransmission.

A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCs

NoCs (Networks-on-chips) are considered as the paradigm of choice for on-chip communication as they solve the scalability concerns of traditional buses. Many research efforts have been aimed toward the design of adaptive routing algorithms that are flexible enough to avoid congested and defective areas in a NoC. However, to avoid deadlocks, most of these solutions either prohibit some turns, which limits path diversity and reduces fault-tolerance, or restrict the use of some virtual channels, which can enable full adaptiveness at the cost of an underutilization of virtual channels. In this work, we eliminate the trade-off between path diversity and virtual channel utilization by introducing a novel, topology-agnostic, deadlock-free routing algorithm capable of taking full advantage of virtual channels for performance boosting while providing very high fault-tolerance at the same time. Both an intuitive and a formal description of our routing algorithm are presented, and simulation results show the merits of our solution compared to other techniques from the literature.

MUGEN: A high-performance fault-tolerant routing algorithm for unreliable Networks-on-Chip

NoCs (Networks-on-Chip) are an attractive alternative to communication buses for SoCs (Systems-on-Chip) as they offer both high scalability and low power consumption. However, designing such systems in the nanoscale era brings up some serious concerns about reliability. Our aim is to design robust NoCs while limiting performance degradation. In this paper, we introduce several techniques meant to increase the reliability and performance of NoCs. We combine these techniques to build a fault-tolerant, deadlock-free and congestion-aware routing algorithm called MUGEN. The algorithm comprises an optimized method to exchange messages between different virtual channel classes, a selection function that uses distant router link information to avoid dead-ends and a new congestion metric used to guide routing decisions towards less congested areas. We simulate an 8×8 Mesh NoC with fault injection to evaluate each method used by MUGEN individually before comparing the full algorithm with existing works from literature. We present promising results about the proposed techniques both in terms of fault-tolerance and performance.

On route table computation strategies in Delay-Tolerant Satellite Networks

Abstract Delay-Tolerant Networking (DTN) has been proposed for satellite networks with no expectation of continuous or instantaneous end-to-end connectivity, which are known as Delay-Tolerant Satellite Networks (DTSNs). Path computation over large and highly-dynamic yet predictable topologies of such networks requires complex algorithms such as Contact Graph Routing (CGR) to calculate route tables, which can become extremely large and limit forwarding performance if all possible routes are considered. In this work, we discuss these issues in the context of CGR and propose alternatives to the existing route computation scheme: first-ending, first-depleted, one-route, and per-neighbor strategies. Simulation results over realistic DTSN constellation scenarios show that network flow metrics and overall calculation effort can be significantly improved by adopting these novel route table computation strategies.

Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs

3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. In addition, the number of vertical paths can be expected to be further reduced due to defects and runtime failures. To reliably route packets under such conditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected 3D-NoCs named “Rout3D”. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the East and North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layers is available anywhere in the network. We combine our algorithm with a novel offline reconfiguration method requiring only 4 bits per router to maintain connectivity upon the occurrence of faults while minimizing the implementation cost. Simulation results reveal that our algorithm is capable of sustaining a very good level of performance compared to related works, in spite of using less virtual channels.

A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC) topologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV), 3D-NoCs are most likely to include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlock-free routing and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections, commonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several alternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed solution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators, and a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algorithms are compared by simulation to highlight the advantages and disadvantages of each solution under various scenarios, and hardware synthesis results demonstrate the scalability of the proposed approach and its suitability for cost-oriented designs.

A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips

Networks-on-Chips (NoCs) are considered to be the paradigm of choice for on-chip communication and are today widely adopted in many-core systems. Many existing routing solutions make use of virtual channels (VCs) to avoid deadlocks while offering enough routing flexibility to avoid faulty and congested areas in a NoC. However, most of the current solutions rely on an overly restrictive, static partitioning of VCs, which results in an underutilization of their throughput enhancement capabilities. To overcome the limitations of such approaches, we introduce a new sufficient condition of deadlock-freedom that greatly relaxes the restrictions imposed by the classic VC-based deadlock-avoidance methods. The strength of our condition lies in the fact that it is imposed on packets at runtime and does not require any partitioning of virtual channels, which makes it possible to fully exploit them to reduce packet blocking and boost performance. Based on this condition, we present a generic, topology-agnostic routing algorithm design methodology that can be used to construct highly flexible routing algorithms in only a few steps. Several examples are presented to showcase the usefulness of our approach for the construction of fault-tolerant routing algorithms, as well as the enhancement and the proof of existing routing algorithms. The implementation of all the required mechanisms in hardware is also described in detail, thereby demonstrating its feasibility in an on-chip environment.

MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips

With NoCs (Networks-on-Chips) becoming a central part of todays many-core systems, ensuring a good level of performance at the routing level has never been so crucial. In previous works, we have introduced a novel method for designing fully adaptive deadlock-free routing algorithms for NoCs called ESPADA (EScape PAths with Dynamic channel Acquisition). The strength of our approach lies in its ability to simultaneously utilize the available virtual channels for throughput enhancement and deadlock-avoidance, thereby enabling high-coverage fault-tolerance at a much higher performance than state-of-the art techniques. In this paper, we further highlight the potentials of this approach and its suitability for low-cost designs, by using it to build MINI-ESPADA, an enhanced version of the popular DyXY algorithm that routes packets following available minimal paths while exploiting the properties of ESPADA to offer higher throughput. In addition to a significant performance improvement, we report a negligible area overhead with respects to the classic XY and DyXY when using the same number of virtual channels.