Nacer-Eddine Zergainoh

An efficient architecture model for systematic design of application-specific multiprocessor SoC

In this paper, we present a novel approach for the design of application specific multiprocessor systems-on chip. Our approach is based on a generic architecture model which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of applications. In addition, it allows one accelerate the design cycle. This paper focuses on the definition of the architecture model and the systematic design flow that can be automated. The feasibility and effectiveness of this approach are illustrated by two significant demonstration examples.

Multilanguage design of heterogeneous systems

Multilanguage solutions are required for the design of heterogeneous systems where different parts belong to different application classes, e.g. control/data or continuous/discrete. The main problem that needs to be solved when dealing with multilanguage design is the refinement of communication between heterogeneous subsystems. This paper discusses the basic concepts of multilanguage design and introduces MUSIC a multilanguage design approach. The paper also shows the application of this approach in the case of a mechatronic system.

Combining a performance estimation methodology with a hardware/software codesign flow supporting multiprocessor systems

This paper addresses performance estimation and architecture exploration issues within the context of hardware/software codesign. We introduce a new methodology to rapidly explore the large design space encountered in hardware/software systems. The proposed methodology is based on a fast and accurate estimation approach. This estimation approach takes advantage of both system and RT levels of abstraction, and combines both static and dynamic analysis techniques, in order to obtain the best trade-off between speed and accuracy. It has been implemented as an extension to a hardware/software codesign flow to enable the exploration of a large number of multiprocessor architecture solutions from the very start of the design process. The effectiveness of the proposed methodology is illustrated by a significant application example. Experimental results indicate strong advantages of the proposed methodology.

A fault-tolerant deadlock-free adaptive routing for on chip interconnects

Future applications will require processors with many cores communicating through a regular interconnection network. Meanwhile, the Deep submicron technology foreshadows highly defective chips era. In this context, not only fault-tolerant designs become compulsory, but their performance under failures gains importance. In this paper, we present a deadlock-free fault-tolerant adaptive routing algorithm featuring Explicit Path Routing in order to limit the latency degradation under failures. This is particularly interesting for streaming applications, which transfer huge amount of data between the same source-destination pairs. The proposed routing algorithm is able to route messages in the presence of any set of multiple nodes and links failures, as long as a path exists, and does not use any routing table. It is scalable and can be applied to multicore chips with a 2D mesh core interconnect of any size. The algorithm is deadlock-free and avoids infinite looping in fault-free and faulty 2D meshes. We simulated the proposed algorithm using the worst case scenario, with different failure rates. Experimentation results confirmed that the algorithm tolerates multiple failures even in the most extreme failure patterns. Additionally, we monitored the interconnect traffic and average latency for faulty cases. For 20×20 meshes, the proposed algorithm reduces the average latency by up to 50%.

Scheduler implementation in MP SoC design

In the design of a heterogeneous multiprocessor system on chip, we face a new design problem; scheduler implementation. In this paper, we present an approach to implementing a static scheduler, which controls all the task executions and communication transactions of a system according to a pre-determined schedule. For the scheduler implementation, we consider both intra-processor and inter-processor synchronization. We also consider scheduler overhead, which is often neglected. In particular, we address the issue of centralized implementation versus distributed implementation. We investigate the pros and cons of the two different scheduler implementations. Through experiments with synthetic examples and a real world multimedia application, we show the effectiveness of our approach.

Design space exploration for hardware/software codesign of multiprocessor systems

We present a new methodology to rapidly explore the large design space encountered in hardware/software systems. The proposed methodology is based on a fast and accurate estimation approach. It has been implemented as an extension to a hardware/software codesign flow to enable the exploration of a large number of multiprocessor architecture solutions from the very start of the design process. The effectiveness of this approach is illustrated by a significant application example.

Towards design and validation of mixed-technology SOCs

This paper illustrates an approach to design and validation of heterogeneous systems. The emphasis is placed on devices which incorporate MEMS parts in either a single mixed-technology (CMOS + micromachining) SOC device, or alternatively as a hybrid system with the MEMS part in a separate chip. The design flow is general, and it is illustrated for the case of applications embedding CMOS sensors. In particular, applications based on finger-print recognition are considered since a rich variety of sensors and data processing algorithms can be considered. A high level multi-language/multi-engine approach is used for system specification and co-simulation. This also allows for an initial high-level architecture exploration, according to performance and cost requirements imposed by the target application. Thermal simulation of the overall device, including packaging, is also considered since this can have a significant impact in sensor performance. From the selected system specification, the actual architecture is finally generated via a multi-language co-design approach which can result in both hardware and software parts. The hardware parts are composed of available IP cores. For the case of a single chip implementation, the most important issue of embedded-core-based testing is briefly considered, and current techniques are adapted for testing the embedded cores in the SOC devices discussed.

Hardware/Software Codesign of On-chip Communication Architecture for Application- Specific Multiprocessor System-On-Chip

System-on-chip (SoC) is developing as a new paradigm in electronic system design. This allows an entire hardware/software system to be built on a single chip, using predesigned components. This paper examines the achievements and future of novel approach and flow for an efficient design of application-specific multiprocessor system-on-chip (called GAM-SoC). The approach is based on a generic architecture model, which is used as a template throughout the design process. The key characteristics of this model are its great modularity, flexibility and scalability, which make it reusable for a large class of applications. In the flow, architectural parameters are first extracted from a high-level system specification and then used to instantiate architectural components, such as processors, memory modules, IP-hardware blocks and on-chip communication networks. The flow includes the generation of hardware/software wrappers that adapts the processor to the on-chip communication network in an application-specific way. The feasibility and effectiveness of this approach are illustrated by significant demonstration examples.

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design

On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip communication network, communication interfaces of processor/IP/memory, on-chip memory, etc.). For an efficient exploration of its design space, we need fast scheduling and timing analysis. In this work, we tackle two problems (one for SW and the other for HW) in on-chip communication design. One is to incorporate the dynamic behavior of SW (interrupt processing and context switching) into on-chip communication scheduling. The other is to reduce on-chip data storage required for on-chip communication, by sharing physical communication buffers with different communication transactions. To solve the problems, we present both ILP (integer linear programming) formulation and heuristic algorithm, which enable the designer to perform efficient on-chip communication scheduling and obtain accurate timing information. Experimental results show the effectiveness of our work.

Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor

Soft errors have been emerged as an important reliability concern of modern ICs. In this work we have implemented an efficient error detection scheme in a low power DSP/MCU processor. Our scheme achieves high error detection efficiency at low hardware cost by means of an original combination of double-sampling and latch based-design into the so-called GRAAL architecture. The implementation of our design in 65nm and 45nm process nodes has confirmed the advantages of the GRAAL architecture: low area and power penalties and negligible performance degradation. Its high error detection efficiency was demonstrated by performing extensive simulations of single-event transients (SETs).