Alexandre Coelho

Detailed and highly parallelizable cycle-accurate network-on-chip simulation on GPGPU

As the number of processing elements in modern chips keeps increasing, the evaluation of new designs will need to account for various challenges at the NoC level. To cope with the impractically long run times when simulating large NoCs, we introduce a novel GPU-based parallel simulation method that can speed up simulations by over 250×, while offering RTL-like accuracy. These promising results make our simulation method ideal for evaluating future NoCs comprising thousands of nodes.

On the Robustness of Stochastic Bayesian Machines

This paper revisits the stochastic computing paradigm as a way to implement architectures dedicated to probabilistic inference. In general, it is assumed the operation over stochastic bit streams is robust with respect to radiation transient events effects. Moreover, it can be expected that leveraging the stochastic computing paradigm to implement probabilistic computations such as Bayesian inference implemented in hardware could yield an increased resilience to radiation effects comparatively to deterministic procedures. However, the practical assessment of the robustness against radiation is mandatory before considering stochastic Bayesian machines (SBMs) in hazardous environments. Results of fault injection campaigns at register transfer level provide the first evidences of the intrinsic robustness of SBMs with respect to single event upsets and single event transients.

Preliminary results of NETFI-2: An automatic method for fault injection on HDL-based designs

Fault injection is a well-known technique to evaluate the susceptibility of integrated circuits to the effects of radiation. In this work, an existing emulation-based methodology is extended, updated and improved under the name of NETFI-2. Preliminary results show that NETFI-2 provides accurate measurements while improving the execution time of the experiment by more than 300% compared with other simulation-based campaigns.

Rout3D: A lightweight adaptive routing algorithm for tolerating faulty vertical links in 3D-NoCs

3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3D Network-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connected NoCs, in which only a few vertical TSV links are available, have been gaining relevance. In addition, the number of vertical paths can be expected to be further reduced due to defects and runtime failures. To reliably route packets under such conditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected 3D-NoCs named “Rout3D”. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the East and North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layers is available anywhere in the network. We combine our algorithm with a novel offline reconfiguration method requiring only 4 bits per router to maintain connectivity upon the occurrence of faults while minimizing the implementation cost. Simulation results reveal that our algorithm is capable of sustaining a very good level of performance compared to related works, in spite of using less virtual channels.

A Framework for Scalable TSV Assignment and Selection in Three-Dimensional Networks-on-Chips

3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC) topologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV), 3D-NoCs are most likely to include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlock-free routing and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections, commonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several alternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed solution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators, and a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algorithms are compared by simulation to highlight the advantages and disadvantages of each solution under various scenarios, and hardware synthesis results demonstrate the scalability of the proposed approach and its suitability for cost-oriented designs.

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

As a relevant communication structure for integrated circuits, Network-on-Chip (NoC) architecture has attracted a range of research topics. Compared to conventional bus technology, NoC provides higher scalability and enhances the system performance for future System-on-Chip (SoC). Divergently, we presented the packet-switching router design for 2D NoC which supports 2D mesh topology. Despite the offered benefits compared to conventional bus technology, NoC architecture faces some limitations such as high cost communication, high power consumption and inefficient router pipeline usage. One of the proposed solutions is 3D design. In this context, we suggest router architecture for 3D mesh NoC, a natural extension of our prior 2D router design. The proposal uses the wormhole switching and employs the turn mod negative-first routing algorithm Thus, deadlocks are avoided and dynamic arbiter are implemented to deal with the Quality of Service (QoS) expected by the network. We also adduce an optimization technique for the router pipeline stages. We prototyped the proposal on FPGA and synthesized under Synopsys tool using the 28 nm technology. Results are delivered and compared with other famous works in terms of maximal clock frequency, area, power consumption and estimated peak performance.

A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips

Networks-on-Chips (NoCs) are considered to be the paradigm of choice for on-chip communication and are today widely adopted in many-core systems. Many existing routing solutions make use of virtual channels (VCs) to avoid deadlocks while offering enough routing flexibility to avoid faulty and congested areas in a NoC. However, most of the current solutions rely on an overly restrictive, static partitioning of VCs, which results in an underutilization of their throughput enhancement capabilities. To overcome the limitations of such approaches, we introduce a new sufficient condition of deadlock-freedom that greatly relaxes the restrictions imposed by the classic VC-based deadlock-avoidance methods. The strength of our condition lies in the fact that it is imposed on packets at runtime and does not require any partitioning of virtual channels, which makes it possible to fully exploit them to reduce packet blocking and boost performance. Based on this condition, we present a generic, topology-agnostic routing algorithm design methodology that can be used to construct highly flexible routing algorithms in only a few steps. Several examples are presented to showcase the usefulness of our approach for the construction of fault-tolerant routing algorithms, as well as the enhancement and the proof of existing routing algorithms. The implementation of all the required mechanisms in hardware is also described in detail, thereby demonstrating its feasibility in an on-chip environment.

MINI-ESPADA: A low-cost fully adaptive routing mechanism for Networks-on-Chips

With NoCs (Networks-on-Chips) becoming a central part of todays many-core systems, ensuring a good level of performance at the routing level has never been so crucial. In previous works, we have introduced a novel method for designing fully adaptive deadlock-free routing algorithms for NoCs called ESPADA (EScape PAths with Dynamic channel Acquisition). The strength of our approach lies in its ability to simultaneously utilize the available virtual channels for throughput enhancement and deadlock-avoidance, thereby enabling high-coverage fault-tolerance at a much higher performance than state-of-the art techniques. In this paper, we further highlight the potentials of this approach and its suitability for low-cost designs, by using it to build MINI-ESPADA, an enhanced version of the popular DyXY algorithm that routes packets following available minimal paths while exploiting the properties of ESPADA to offer higher throughput. In addition to a significant performance improvement, we report a negligible area overhead with respects to the classic XY and DyXY when using the same number of virtual channels.

SEU impact in processor's control-unit: Preliminary results obtained for LEON3 soft-core

The miniaturization issues from the advanced integrated circuit manufacturing technologies lead to increase the probabilities of single node upset and multiple upsets errors of neighbor nodes. The study of such conjecture is mandatory to specify the protection requirements. This paper deals with the study of such single and multiple errors due to the impact of a single particle in the control unit of complex devices such as processors. Because the layout of the studied device cannot be anticipated, the nodes neighborhood is thus unknown. To deal with this issue, this work presents the results of both exhaustive and random fault-injection experiments performed at register transfer level (RTL) and targeting the control bits of LEON3 processor. Fault injection is achieved by means an automatic netlist fault injection tool called NETFI-2.