Amirkoushyar Ziabari

Minimizing thermally induced interfacial shearing stress in a thermoelectric module with low fractional area coverage

The problem of minimizing the level of the thermally induced interfacial shearing stress in a Thermo-Electric Module (TEM) is addressed using analytical and finite-element-analysis (FEA) based modeling. The maximum stress is calculated for different leg sizes. Good agreement between the analytical and FEA predictions has been found. It is concluded that the shearing stress can be effectively minimized by using thinner legs with compliant interfaces.

Fast thermal simulators for architecture level integrated circuit design

High temperatures and non-uniform temperature distributions have become a serious concern since they limit both performance and reliability of Integrated Circuits (IC). With computer architects concern to position microarchitecture blocks in a processor, faster thermal models can be developed at the cost of hiding finer grain details such as circuit or transistor level information. Several methods to quickly estimate the surface temperature profiles of microarchitecture blocks have been investigated in recent years. HotSpot simulator is widely used in computer architecture community. SESCTherm is another architecture level thermal simulator which has shown good performance and modularity in modeling. Recently Power Blurring (PB) method has been developed for both steady-state and transient thermal analysis of standard and 3D chips. While some of these methods are validated against finite element and Greens function based techniques, there are no detailed comparisons of the accuracy and speed for some common applications. In this paper we present the steady-state and transient temperature distributions calculated by these three architecture level thermal simulators. A detailed comparison taking into account the accuracy and the computation speed is performed. Our results indicate that Power Blurring has the potential to be a promising architecture level thermal simulator for fast calculation of temperature profile from the input power map in a realistic package which, in turn, is a key ingredient for full self-consistent simulations.

Power Blurring: Fast Static and Transient Thermal Analysis Method for Packaged Integrated Circuits and Power Devices

High-temperature and temperature nonuniformity in high-performance integrated circuits (ICs) can significantly degrade chip performance and reliability. Thus, accurate temperature information is a critical factor in chip design and verification. Conventional volume grid-based techniques, such as finite-difference and finite-element methods (FEMs), are computationally expensive. In an effort to reduce the computation time, we have developed a new method, called power blurring (PB), for calculating temperature distributions using a matrix convolution technique in analogy with image blurring. The PB method considers the finite size and boundaries of the chip as well as 3-D heat spreading in the heat sink. PB is applicable to both static and transient thermal simulations. Comparative studies with a commercial FEM tool show that the PB method is accurate within 2%, with orders of magnitude speedup compared with FEM methods. PB can be applied to very fine power maps with a grid size as small as 10 μm for a fully packaged IC or submicrometer heat sources in power electronic transistor arrays. In comparison with architecture-level thermal simulators, such as HotSpot, PB provides much more accurate temperature profiles with reduced computation time.

Fast thermal simulations of vertically integrated circuits (3D ICs) including thermal vias

A fast convolution-based technique, deemed Power Blurring, is demonstrated for thermal analysis of 3D ICs, including thermal vias. The temperature resulting from any power may in each layer of the chip can be computed without the need to re-mesh the whole structure. The maximum error in estimation time is reduced by a factor of 76× compared to finite element software.

Energy efficient liquid-thermoelectric hybrid cooling for hot-spot removal

We report a study on a liquid-thermoelectric hybrid cooling that allows a multiple larger heat flux (>;600 W/m2) hotspots on a chip that is never achievable with a reasonable pump power for a microchannel with single phase liquid cooling. Thermoelectric effect is realized in this study by embedding to the silicon chip in superlattice microcooler which has been studied in our previous work. We went through an analytic modeling including spreading resistance through the substrate and modeled the fluid dynamic characteristic of microchannel so that we were able to find the pump power and cooling power of superlattice cooler. We also verified the performance with 3D numerical simulation. The results show that the hybrid system allows much higher heat flux for a hotspot while superlattice cooler locates correctly. As an example, if we have a ZT=0.5 material, a 500μm × 500μm hotspot can be maintained at 85°C (ambient 35°C) with around 850W/cm2 while a simple liquid cooling reaches 620W/cm2 for the same 12W/cm2 of overall cooling power.

Stable thermoreflectance thermal imaging microscopy with piezoelectric position control

Thermoreflectance thermal imaging microscopy is based on very small change in the surface reflection as a function of temperature. Image shift and instrument drift are limiting factors to obtain accurate and reproducible thermal images. Under large magnification and for devices with sizes on the order of hundreds of nanometers, image registration could significantly encumber accurate thermoreflectance measurements. Additionally, image blurring is an issue because of small sample movements during the measurement. The problem of image registration and defocusing is particularly important during the calibration process to extract the thermoreflectance coefficient of the materials under study. Calibration requires changing the sample temperature with an external stage, which causes significant movement due to heat expansion from the stage. In this work, we discuss how the image registration and defocusing affect accurate measurement and calibration in thermoreflectance thermal imaging. We also show that by incorporating and controlling the position of the sample under test with a closed-loop piezo-stage one can perform accurate and reproducible thermal measurement. Using this setup, we measured the coefficient of thermoreflectance (CTR) of gold at several wavelengths and under different magnifications. We present for the first time thermoreflectance calibration of feature sizes below the diffraction limit, on the order of 200nm.

High temperature thermoreflectance imaging and transient Harman characterization of thermoelectric energy conversion devices

Advances in thin film growth technology have enabled the selective engineering of material properties to improve the thermoelectric figure of merit and thus the efficiency of energy conversion devices. Precise characterization at the operational temperature of novel thermoelectric materials is crucial to evaluate their performance and optimize their behavior. However, measurements on thin film devices are subject to complications from the growth substrate, non-ideal contacts, and other thermal and electrical parasitic effects. In this manuscript, we determine the cross-plane thermoelectric material properties in a single measurement of a 25 μm InGaAs thin film with embedded ErAs (0.2%) nanoparticles using the bipolar transient Harman method in conjunction with thermoreflectance thermal imaging at temperatures up to 550 K. This approach eliminates discrepancies and potential device degradation from the multiple measurements necessary to obtain individual material parameters. In addition, we present a strat...

Enabling power density and thermal-aware floorplanning

With temperature being one of the main limiting factors in design of high performance processors, early evaluation of thermal effects in design stages is becoming a necessity. Floorplanning is an imperative step in the design process where thermal effects can be taken into account. This work studies a thermal-aware floorplanning scheme, with the goal of increasing both reliability and performance measures of the design. We show that a majority of thermal emergencies can be averted by a) leveraging the lateral heat transfer effects (as has been shown previously), and b) by reducing the power density of thermally critical blocks. The former becomes possible through moving, and modifying the aspect-ratio of the blocks in the floorplanning process. The latter, one of the key contributions of this work, is carried out through resizing of functional blocks in a controlled way. We also propose a selective power map generation method for the floorplanning process. In this method the time windows in which thermal emergencies occur guide the power map generation. As a result, we observed an 8.8% performance improvement, and a 40% reliability increase with the area overhead of just 3%.

Thermoreflectance CCD Imaging of Self-Heating in Power MOSFET Arrays

Thermoreflectance imaging with high spatial resolution is used to inspect self-heating distribution in active high power (4A) metal-oxide-semiconductor field-effect transistor transistor arrays designed for high-frequency (MHz) operation. Peak temperature change and self-heating distribution is analyzed for both low- and high-dc bias cases and for different ambient die temperatures (296-373 K). Thermoreflectance images reveal temperature nonuniformity greater than a factor of two over the full area of the transistor arrays. Thermal nonuniformity is revealed to be strongly dependent on both bias level and ambient die temperature. Verification based on the fine grain power dissipation in the transistor array was performed using the R3D method for electrical simulation and power blurring for thermal simulation. Results demonstrate thermoreflectance imaging as an effective tool for fast submicrometer noncontact thermal characterization of active power devices.

Full-field thermal imaging of quasiballistic crosstalk reduction in nanoscale devices

Understanding nanoscale thermal transport is of substantial importance for designing contemporary semiconductor technologies. Heat removal from small sources is well established to be severely impeded compared to diffusive predictions due to the ballistic nature of the dominant heat carriers. Experimental observations are commonly interpreted through a reduction of effective thermal conductivity, even though most measurements only probe a single aggregate thermal metric. Here, we employ thermoreflectance thermal imaging to directly visualise the 2D temperature field produced by localised heat sources on InGaAs with characteristic widths down to 100 nm. Besides displaying effective thermal performance reductions up to 50% at the active junctions in agreement with prior studies, our steady-state thermal images reveal that, remarkably, 1–3 μm adjacent to submicron devices the crosstalk is actually reduced by up to fourfold. Submicrosecond transient imaging additionally shows responses to be faster than conventionally predicted. A possible explanation based on hydrodynamic heat transport, and some open questions, are discussed.When thermal fields in semiconductors approach the submicron scale, non-diffusive heat transport is observed where Fourier based heat transport models fail. Here, the authors use thermal imaging to visualise these thermal field variations and in turn derive a hydrodynamic heat transport model.