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Dive into the research topics where Amit Khanna is active.

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Featured researches published by Amit Khanna.


Proceedings of SPIE | 2015

Imec iSiPP25G silicon photonics: a robust CMOS-based photonics technology platform

Philippe Absil; Peter De Heyn; Hongtao Chen; Peter Verheyen; Guy Lepage; Marianna Pantouvaki; Jeroen De Coster; Amit Khanna; Youssef Drissi; Dries Van Thourhout; Joris Van Campenhout

Silicon photonics has become in the past years an important technology adopted by a growing number of industrial players to develop their next generation optical transceivers. However most of the technology platforms established in CMOS fabrication lines are kept captive or open to only a restricted number of customers. In order to make silicon photonics accessible to a large number of players several initiatives exist around the world to develop open platforms. In this paper we will present imec’s silicon photonics active platform accessible through multi-project wafer runs.


Optics Express | 2014

Impact of ALD grown passivation layers on silicon nitride based integrated optic devices for very-near-infrared wavelengths

Amit Khanna; Ananth Subramanian; Markus Häyrinen; Shankar Kumar Selvaraja; Peter Verheyen; Dries Van Thourhout; Seppo Honkanen; Harri Lipsanen; Roel Baets

A CMOS compatible post-processing method to reduce optical losses in silicon nitride (Si(3)N(4)) integrated optical waveguides is demonstrated. Using thin layer atomic layer deposition (ALD) of aluminum oxide (Al(2)O(3)) we demonstrate that surface roughness can be reduced. A 40 nm thick Al(2)O(3) layer is deposited by ALD over Si(3)N(4) based strip waveguides and its influence on the surface roughness and the waveguide loss is studied. As a result, an improvement in the waveguide loss, from very high loss (60 dB/cm) to low-loss regime (~5 dB/cm) is reported for a 220 nm x 500 nm Si(3)N(4) wire at 900 nm wavelength. This opens prospects to implement very low loss waveguides.


Integrated Photonics: Materials, Devices, and Applications II, 24-26 April 2013, Grenoble, France, 8767 | 2013

ePIXfab: the silicon photonics platform

Amit Khanna; Youssef Drissi; Pieter Dumon; Roel Baets; Philippe Absil; J. Pozo; D.M.R. Lo Cascio; Maryse Fournier; J.-M. Fedeli; L Fulbert; Lars Zimmermann; B. Tillack; T. Aalto; Peter O'Brien; D. Deptuck; J. Xu; D. Gale

ePIXfab-The European Silicon Photonics Support Center continues to provide state-of-the-art silicon photonics solutions to academia and industry for prototyping and research. ePIXfab is a consortium of EU research centers providing diverse expertise in the silicon photonics food chain, from training users in designing silicon photonics chips to fiber pigtailed chips. While ePIXfab provides world-wide users access to advanced silicon photonics it also focuses its attention to expanding the silicon photonics infrastructure through a network of design houses, access partners and industrial collaborations.


international conference on transparent optical networks | 2012

ESSenTIAL: EPIXfab services specifically targeting (SME) industrial takeup of advanced silicon photonics

J. Pozo; P. Kumar; D.M.R. Lo Cascio; Amit Khanna; Pieter Dumon; Danaë Delbeke; Roel Baets; Maryse Fournier; J.-M. Fedeli; L Fulbert; Lars Zimmermann; B. Tillack; H. Tian; T. Aalto; Peter O'Brien; D. Deptuck; J. Xu; Xiyun Zhang; D. Gale

ePIXfab brings silicon photonics within reach of European small and medium sized enterprises, thereby building on its track record and its integration into Europractice. To this end, ePIXfab offers affordable access to standardized active and passive silicon photonic IC and packaging technology, a path from design to manufacturing and hands-on training. Based on a consortium of major research institutes with silicon photonics expertise, ePIXfab reaches out to European industry and supports them to evaluate silicon photonics in the context of concrete applications and markets. In order to ensure low-cost, quick access and scalability to manufacturing, the maturity of silicon photonic IC technology is enhanced by setting up a library of generic devices, a level of process and device benchmarking and a well maintained design flow. For the first time, devices in a standard package are offered to facilitate measurements. Training programs on the IC and packaging services are also offered, including hands-on training in making designs. Maturity, standardization and sustainability are driven by a steadily growing worldwide user base.


Archive | 2016

CMOS Cost–Volume Paradigm and Silicon Photonics Production

Amit Khanna; Dieter Bode; Carl Das; Philippe Absil; Steve Beckers

A clear fabless path to silicon photonics R&D and low volume production is taking shape. Current low volume requirements in silicon photonics pose a price challenge for products. Further, technical challenges for low volume production also need to be addressed. In this chapter we discuss the rapidly evolving macro-landscape in datacom traffic and its impact on silicon photonics, other applications domains and their volume requirements, and stages in low volume production with their associated challenges.


conference on lasers and electro optics | 2013

Foundry technology and services for Si photonics

Pieter Dumon; Amit Khanna

We discuss the progress in development and offering of silicon photonic integration platforms based on 200mm and 300mm wafer technologies. Devices have capability for developing high-speed datacommunication, but are also used for life science applications.


Silicon photonics III, systems and applications | 2016

Design Flow Automation for Silicon Photonics: Challenges, Collaboration, and Standardization

Mitchell Heins; Chris Cone; John Ferguson; Ruping Cao; James Pond; Jackson Klein; Twan Korthorst; Arjen Bakker; Remco Stoffer; Martin Fiers; Amit Khanna; Wim Bogaerts; Pieter Dumon; Kevin Nesmith

Silicon photonics is nothing new. It has been around for decades, but in recent years, it has gained traction as electronic design challenges increase drastically with their atomic-level limitations. Silicon photonics has made significant advancements during this period, but there are many obstacles without an acceptable level of comfort as seen by the lack of semiconductor community involvement. Apart from a series of technological barriers, such as extreme fabrication sensitivity, inefficient light generation on-chip, etc., there are also certain design challenges. In this chapter, we will discuss the challenges and the opportunities in photonic integrated circuit design software tools, examine existing design flows for photonics design and how these fit different design styles, and review the activities in collaboration and standardization efforts to improve design flows.


european quantum electronics conference | 2009

Non-birefringent cross-slot waveguide

Amit Khanna; Antti Säynätjoki; Ari Tervonen; Seppo Honkanen

Silicon photonics is a rapidly advancing technology [1]. Silicon based slot-waveguides for high optical mode confinement of quasi-TE (vertical slot) and quasi-TM (horizontal slot) mode have been demonstrated independently [2,3]. These structures are highly birefringent, which limits their usability in photonic devices. We propose a non-birefringent structure based on slot waveguides. To present the idea, a symmetric cross-slot waveguide with horizontal and vertical slots with widths, wsh=wsv=60 nm, in a silicon dioxide environment (nSiO2=1.46) is shown in Fig. 1a. The material of the rail is amorphous silicon (na-Si=3.58) with height, wh=300 nm, and width, wr=120 nm. Also shown is the intensity distribution of the quasi-TE mode in the structure, simulated with the Film Mode Matching (FMM) method [4]. As expected, the quasi-TM mode has the same effective index as the TE mode and its mode field is confined into the horizontal slot.


international conference on group iv photonics | 2014

High Q photonic crystal cavities realised using Deep Ultraviolet Lithography

Karl Welna; Kapil Debnath; Pieter Dumon; Amit Khanna; Thomas F. Krauss; Liam O'Faolain


4th International Symposium on Photonics and Electronics Convergence - ISPEC | 2014

Review of a 200mm SOI silicon photonics platform performance for low-power optical integrated circuits development

Philippe Absil; Peter Verheyen; M Pantouvaki; Peter De Heyn; Hongtao Chen; Guy Lepage; Jeroen De Coster; M. Rakowski; Pieter Dumon; Amit Khanna; Günther Roelkens; Roel Baets; Joris Van Campenhout

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Pieter Dumon

Karlsruhe Institute of Technology

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Roel Baets

Information Technology University

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Seppo Honkanen

University of Eastern Finland

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Guy Lepage

Katholieke Universiteit Leuven

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Jeroen De Coster

Katholieke Universiteit Leuven

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Peter De Heyn

Katholieke Universiteit Leuven

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Peter Verheyen

Technische Universität München

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