Amit Mehrotra

Phase noise in oscillators: a unifying theory and numerical methods for characterization

Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields, such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterization. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterization of timing jitter and spectral dispersion, for computing of which we have developed efficient numerical methods. We demonstrate our techniques on a variety of practical electrical oscillators and obtain good matches with measurements, even at frequencies close to the carrier, where previous techniques break down. Our methods are more than three orders of magnitude faster than the brute-force Monte Carlo approach, which is the only previously available technique that can predict phase noise correctly.

A power-optimal repeater insertion methodology for global interconnects in nanometer designs

This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.

Phase noise in oscillators: a unifying theory and numerical methods for characterisation

Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact, nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterisation of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on practical electrical oscillators, and obtain good matches with measurements even at frequencies close to the carrier, where previous techniques break down.

On thermal effects in deep sub-micron VLSI interconnects

This paper presents a comprehensive analysis of the thermal effects in advanced high performance interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge. Technology (Cu, low-k etc.) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration reliability has been analyzed simultaneously, which will have important implications for providing robust and aggressive deep sub-micron interconnect design guidelines. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the upper-level signal lines are investigated.

Analysis of IR-drop scaling with implications for deep submicron P/G network designs

This paper presents a detailed analysis of the power-supply voltage (IR) drop scaling in DSM technologies. For the first time, the effects of temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the IR-drop effect in the power/ground (P/G) network increases rapidly with technology scaling, and using well-known counter measures such as wire-sizing and decoupling capacitor insertion with resource allocation schemes that are typically used in the present designs may not be sufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power lines of switching devices in a clock network can introduce significant amount of skew which in turn degrades the signal integrity.

Phase noise and timing jitter in oscillators

Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. We present a rigorous nonlinear analysis for phase noise in oscillators and reach the following conclusions: the power spectrum of an oscillator does not blow up at the carrier frequency as predicted by many previous analyses. Instead, the shape of the spectrum is a Lorentzian (the shape of the squared magnitude of a one-pole lowpass filter transfer function) about each harmonic. The average spread (variance) of the timing jitter grows exactly linearly with time. A single scalar constant suffices to characterise both the timing jitter and spectral broadening due to phase noise. Previous linear analyses of phase noise make unphysical predictions such as infinite noise power. We develop efficient computational methods in the time and frequency domains for predicting phase noise. Our techniques are practical for large circuits. We obtain good matches between spectra predicted using our technique and measured results, even at frequencies close to the carrier and its harmonics, where most previous techniques break down.

Noise analysis of radio frequency circuits

1. Introduction.- 2. Overview of Existing Techniques.- 3. Perturbation Analysis of Stable Oscillators.- 4. Noise Analysis of Stable Oscillators.- 5. Noise Analysis of Nonautonomous Circuits.- 6. Noise Analysis of Circuits with Multitone Inputs.- 7. Noise Analysis of Phase-Locked Loops.- 8. Conclusions and Future Directions.- Appendices.- Definitions and Solution Techniques of SDEs.- 1 Mathematical Preliminaries.- 2 Ito Integrals.- 3 Stochastic Differential Equations.

Supply and power optimization in leakage-dominant technologies

In this paper, we present a methodology for systematically optimizing the power-supply voltage for either maximizing the performance of very large scale integration (VLSI) circuits or minimizing the power dissipation in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations that describe the transistor behavior as a function of power supply and temperature. We use these models to calculate the full-chip power dissipation as a function of power supply and temperature. We then solve the power and chip thermal equations simultaneously to calculate the chip temperature and power dissipation at a given power supply. By varying the power-supply voltage, we determine the optimum V/sub DD/ value that minimized delay per unit length in global interconnects and therefore maximizes performance. Using the same framework, by again varying the supply we find the optimum V/sub DD/ that minimized the total power dissipation while maintaining a given delay per unit length. We show that for 90- and 65-nm technologies, where leakage power represents a significant fraction of the total power dissipation, optimum V/sub DD/ for maximum performance is lower than the International Technology Roadmap for Semiconductors (ITRS) specified supply voltage. This is due to the fact that reducing V/sub DD/ results in a large reduction in total power dissipation, and therefore the chip temperature, which improves performance. This improvement in performance is greater than the performance penalty incurred due to reduction in V/sub DD/. We also show that as the required delay per unit length is increased, total chip power consumption is reduced significantly if the power supply is also reduced as compared to the case when power supply is fixed at the nominal value. This change becomes larger with technology scaling due to the fact that leakage power, which is a very strong function of chip temperature, becomes a larger fraction of the full-chip power dissipation.

Quantitative projections of reliability and performance for low-k/Cu interconnect systems

This paper presents a methodology for quantitative analysis of the role of electromigration (EM) reliability and interconnect performance in determining the optimal interconnect design in low-k/Cu interconnect systems. It is demonstrated that EM design limits for signal lines are satisfied once interconnect performance is optimized.

Power supply optimization in sub-130 nm leakage dominant technologies

In this paper we present a methodology for systematically optimizing the power supply voltage for maximizing the performance of VLSI circuits in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations which describe the transistor behaviour as a function of power supply, and temperature. We use these models to calculate the full-chip power dissipation as a function of power supply and temperature. We then solve the power and chip thermal equations simultaneously to calculate the chip temperature and power dissipation at a given power supply. By varying the power supply voltage we determine the optimum V/sub DD/ value which minimized delay per unit length in global interconnects and therefore maximizes performance. We show that for 90 nm and 65 nm technologies where leakage power represents a significant fraction of the total power dissipation, Optimum V/sub DD/ is lower than the ITRS specified supply voltage. This is due to the fact that reducing V/sub DD/ results in a large reduction in total power dissipation and therefore the chip temperature which improves performance. This improvement in performance is greater than the performance penalty incurred due to reduction in V/sub DD/.