Amit Narayan

Logic synthesis for large pass transistor circuits

Pass transistor logic (PTL) can be a promising alternative to static CMOS for deep sub-micron design. In this work, we motivate the need for CAD algorithms for PTL circuit design and propose decomposed BDDs as a suitable logic level representation for synthesis of PTL networks. Decomposed BDDs can represent large, arbitrary functions as a multi-stage circuit and can exploit the natural, efficient mapping of a BDD to PTL. A comprehensive synthesis flow based on decomposed BDDs is outlined for PTL design. We show that the proposed approach allows us to make logic-level optimizations similar to the traditional multi- level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on area, delay and power of the final circuit implementation which do not have any equivalent in the traditional approach. We also present a set of heuristical algorithms to synthesize PTL circuits optimized for area, delay and power which are key to the proposed synthesis flow. Experimental results on ISCAS benchmark circuits show that our technique yields PTL circuits with substantial improvements over static CMOS designs. In addition, to the best of our knowledge this is the first time PTL circuits have been synthesized for the entire ISCAS benchmark set.

Reachability analysis using partitioned-ROBDDs

We address the problem of finite state machine (FSM) traversal, a key step in most sequential verification and synthesis algorithms. We propose the use of partitioned ROBDDs to reduce the memory explosion problem associated with symbolic state space exploration techniques. In our technique, the reachable state set is represented as a partitioned ROBDD (A. Narayan et al., 1996). Different partitions of the Boolean space are allowed to have different variable orderings and only one partition needs to be in memory at any given time. We show the effectiveness of our approach on a set of ISCAS89 benchmark circuits. Our techniques result in a significant reduction in total memory utilization. For a given memory limit, partitioned ROBDD based method can complete traversal for many circuits for which monolithic ROBDDs fail. For circuits where both partitioned ROBDDs as well as monolithic ROBDDs cannot complete traversal, partitioned ROBDDs can reach a significantly larger set of states.

Measurement and modeling of MOS transistor current mismatch in analog IC's

This paper presents a new methodology for measuring MOS transistor current mismatch and a new transistor current mismatch model. The new methodology is based on extracting the mismatch information from a fully functional circuit rather than on probing individual devices; this extraction leads to more efficient and more accurate mismatch measurement. The new model characterizes the total mismatch as a sum of two components, one systematic and the other random. For our process, we attribute nearly half of the mismatch to the systematic component, which we model as a linear gradient across the die. Furthermore, we present a new model for the random component of the mismatch which is 60% more accurate, on average, than existing models.

Formal verification of combinational circuits

With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. Simulation based methodologies are generally inadequate to validate the correctness of a design with a reasonable confidence. More and more designers are moving towards formal methods to guarantee the correctness of their designs. In this paper we survey some state-of-the-art techniques used to perform automatic verification of combinational circuits. We classify the current approaches for combinational verification into two categories functional and structural. The functional methods consist of representing a circuit as a canonical decision diagram. Two circuits are equivalent if and only if their decision diagrams are equal. The structural methods consist of identifying related nodes in the circuit and using them to simplify the problem of verification. We briefly describe some of the methods in both the categories and discuss their merits and drawbacks.

A survey of techniques for formal verification of combinational circuits

With the increase in the complexity of present day systems, proving the correctness of a design has become a major concern. Simulation based methodologies are generally inadequate to validate the correctness of a design with a reasonable confidence. More and more designers are moving towards formal methods to guarantee the correctness of their designs. The authors survey some state-of-the-art techniques used to perform automatic verification of combinational circuits. They classify the current approaches for combinational verification into two categories: functional and structural. The functional methods consist of representing a circuit as a canonical decision diagram. Two circuits are equivalent if and only if their decision diagrams are equal. The structural methods consist of identifying related nodes in the circuit and using them to simplify the problem of verification. They briefly describe some of the methods in both the categories and discuss their merits and drawbacks.

Decomposition Techniques for Efficient ROBDD Construction

In this paper, we address the problem of memory-efficient construction of ROBDDs for a given Boolean network. We show that for a large number of applications, it is more efficient to construct the ROBDD by a suitable combination of top-down and bottom-up approaches than a purely bottom-up approach. We first build a decomposed ROBDD of the target function and then follow it by a symbolic composition to get the final ROBDD. We propose two heuristic algorithms for decomposition. One is based on a topological analysis of the given netlist, while the other is purely functional, making no assumptions about the underlying circuit topology. We demonstrate the utility of our methods on standard benchmark circuits as well as some hard industrial circuits. Our results show that this method requires significantly less memory than the conventional bottom-up construction. In many cases, we are able to build the ROBDDs of outputs for which the conventional method fails. In addition, in most cases this memory reduction is accompanied by a significant speed up in the ROBDD construction process.

A study of composition schemes for mixed apply/compose based construction of ROBDDs

Reduced Ordered Binary Decision Diagrams (ROBDDs) have traditionally been built in a bottom-up fashion. In this scheme, the intermediate peak memory utilization is often larger than the final ROBDD size, limiting the complexity of the circuits which can be processed using ROBDDS. Recently we showed that for a large number of applications, the peak memory requirement can be substantially reduced by a suitable combination of bottom up (decomposition based) and top down (composition based) approaches of building ROBDDs. In this paper, we focus on the composition process. We detail four heuristic algorithms for finding good composition orders, and compare their utility on a set of standard benchmark circuits. Our schemes offer a matrix of time-memory tradeoff points.

Steady-state analysis of voltage and current controlled oscillators

This paper introduces the problem of finding the steady-state and the numerical value of the controlling voltage or current for oscillators where the frequency of oscillation is known beforehand. These situations are very common when the oscillator is part of a phase-locked loop (PLL). In PLLs, the reference frequency as well as the divide ratios are known at the time of design. Therefore the desired frequency of the voltage (current) controlled oscillator is known but not the controlling voltage (current). We formulate this problem as the solution of an appropriate nonlinear equation. We present robust and efficient numerical techniques for solving this nonlinear equation both in time and frequency domain. We demonstrate using experimental results that this technique is at par with classical methods of calculating oscillator steady-state and period of oscillation for a given control voltage. We show that compared to a search-based approach to calculating the desired control voltage or current, our direct method is a order of magnitude faster for the same accuracy.

Continuation method in multitone harmonic balance

Design of communication circuits often requires computing quasi-periodic steady state response to multiple inputs of different frequencies that may not always be harmonically related. Multitone harmonic balance method can be used to provide an accurate solution if the circuit is mildly nonlinear. However, the convergence of harmonic balance methods is not guaranteed if the initial guess is far from the actual solution. We present a novel approach to apply continuation method in multitone harmonic balance to significantly improve the convergence properties of this technique. In addition to being more robust, we show that the continuation based method can be significantly more efficient in terms of run-time compared to traditional fixed step source-stepping methods. Simulation results on strongly nonlinear circuits are used to illustrate the effectiveness of the algorithm.