Kartikeya Mayaram

Analysis of charge-pump phase-locked loops

In this paper, we present an exact analysis for third-order charge-pump phase-locked loops using state equations. Both the large-signal lock acquisition process and the small-signal linear tracking behavior are described using this analysis. The nonlinear state equations are linearized for the small-signal condition and the z-domain noise transfer functions are derived. A comparison to some of the existing analysis methods such as the impulse-invariant transformation and s-domain analysis is provided. The effect of the loop parameters and the reference frequency on the loop phase margin and stability is analyzed. The analysis is verified using behavioral simulations in MATLAB and SPECTRE.

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL

A scalable substrate noise coupling model for design of mixed-signal IC's

This paper describes a design-oriented scalable macromodel for substrate noise coupling in heavily-doped substrates. The model requires only four parameters which can be readily extracted from a small number of device simulations or measurements. Once these parameters have been determined, the model can be used in design for any spacing between the injection and sensing contacts and for different contact geometries. The scalability of the model with separation and width provides insight into substrate coupling and optimization issues prior to and during the layout phase. The model is validated with measurements from test structures fabricated in a 0.5 /spl mu/m CMOS process. Applications of the model to circuit design are demonstrated with simulation results.

A Digital PLL With a Stochastic Time-to-Digital Converter

A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13-mum CMOS process, features a 0.7-1.7-GHz oscillator tuning range and a 6.9-ps rms jitter, and consumes 17 mW under 1.2-V supply while operating at 1.2 GHz.

Computer-aided circuit analysis tools for RFIC simulation: algorithms, features, and limitations

The design of the radio frequency (RF) section in a communication integrated circuit (IC) is a challenging problem. Although several computer-aided analysis tools are available for RFIC design, they are not effectively used, because there is a lack of understanding about their features and limitations. These tools provide fast simulation of RFICs. However, no single tool delivers a complete solution for RFIC design. This paper describes the shortcomings of conventional SPICE-like simulators and the analyses required for RF applications with an emphasis on accurate and efficient simulation of distortion and noise. Various analysis methods, such as harmonic balance, shooting method, mixed frequency-time methods, and envelope methods, that are currently available for RFIC simulation are presented. Commercial simulators are compared in terms of their functionalities and limitations. The key algorithmic features and the simulator-specific terminology are described.

Self-heating effects in basic semiconductor structures

Investigates the effects of self-heating on the high current I-V characteristics of semiconductor structures using a fully coupled electrothermal device simulator. It is shown that the breakdown in both resistors and diodes is caused by conductivity modulation due to minority carrier generation. In isothermal simulations with T=300 K, avalanche generation is the source of minority carriers. In simulations with self-heating, both avalanche and thermal generation of minority carriers can contribute to the breakdown mechanism. The voltage and current at breakdown are dependent on the structure of the device and the doping concentration in the region with lower doping. For all structures, except highly doped resistors with poor heating sinking at the contacts, the temperature at thermal breakdown ranged from 1.25T/sub i/ to 3T/sub i/, where T/sub i/ is the temperature at which the semiconductor goes intrinsic. Hence, it is found that T=T/sub i/ is not a general condition for thermal (or second) breakdown. From these studies, an improved condition for thermal breakdown is proposed. >

Method for a Constant Loop Bandwidth in LC-VCO PLL Frequency Synthesizers

An LC-VCO based phase-locked loop (PLL) frequency synthesizer which incorporates loop bandwidth tracking is described. In order to minimize loop bandwidth variations resulting from changes in the LC-VCO gain, the proposed PLL employs an averaging varactor based split-tuned LC-VCO and a servo loop which sets the charge-pump current to be inversely proportional to the square of the oscillation frequency. The combination of these techniques maintains a constant loop bandwidth over a wide range of operating frequencies. Fabricated in a 0.13 mum CMOS technology, the prototype chip measures less than plusmn4% variation in KVCOmiddotICP / N (equivalent to the variation in PLL loop bandwidth) for an operating frequency range of 3.1 to 3.9 GHz.

A simple subcircuit extension of the BSIM3v3 model for CMOS RF design

An accurate and simple lumped-element extension of the BSIM3v3 MOSFET model for small-signal radio-frequency circuit simulation is proposed and investigated. Detailed comparisons of the small-signal y and s parameters with both two-dimensional device simulations and measurement data are presented. A procedure is developed to extract the values of two lumped resistors-the only added elements. The non-quasi-static and substrate effects can be modeled with these two resistors to significantly improve the model accuracy up to a frequency of 10 GHz, which is about 70% of the f/sub T/ of the 0.5 /spl mu/m NMOS transistor.

An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators

A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design measures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the measured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm2

A model for the electric field in lightly doped drain structures

A semi-quantitative model for the lateral channel electric field in LDD MOSFETs has been developed. This model is derived from a quasi-two-dimensional analysis under the assumption of a uniform doping profile. A field reduction factor and voltage improvement, indicating the effectiveness of an LDD design in reducing the peak channel field, are used to compare LDD structures with, without, and with partial gate/drain overlap. Approximate equations have been derived that show the dependencies of the field reduction factor on bias conditions and process parameters. Plots showing the trade-off between, and the process-dependencies of, the field reduction factor/voltage improvement and the series resistance are presented for the three cases. Structures with gate-drain overlap are found to provide greater field reduction than those without the overlap for the same series resistance introduced. This should be considered when comparing the double-diffused and spacer LDD structures. It is shown that gate-drain offset can cause the rise of channel field and substrate current at large gate voltages. This offset is also found to be responsible for nonsaturation of drain current. The model has also been compared with two-dimensional simulation results.