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Dive into the research topics where Amiya Nayak is active.

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Featured researches published by Amiya Nayak.


[1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium | 1990

Fault-intolerance of reconfigurable systolic arrays

Amiya Nayak; Nicola Santoro; Richard Tan

Identification, characterization, and construction of fault patterns that are catastrophic for linear systolic arrays are discussed. It is shown that for a given link configuration in the array, it is possible to identify all PE (processing element) catastrophic fault patterns. The requirement on the minimum number of faults in a fault pattern and its spectrum (spread out) for it to be catastrophic is shown to be a function of the length of the longest bypass link available, and not of the total number of bypass links. The paper also gives bounds on the width of a catastrophic fault spectrum.<<ETX>>


Integration | 1993

Efficient construction of catastrophic patterns for VLSI reconfigurable arrays

Amiya Nayak; Linda Pagli; Nicola Santoro

Abstract Patterns of faults occuring at strategic locations may render an entire VLSI system unusable regardless of its component redundancy and of its reconfiguration capabilities. The characterization of such patterns is obviously crucial for the identification, testing and detection of catastrophic events. The fault patterns that are catastrophic for regular architectures, particularly the systolic arrays, have been extensively studied. For a given link configuration, there are many fault patterns which are catastrophic. Among those, there is a particular fault pattern, called the reference fault pattern , which is crucial for the development of testing techniques; furthermore, the efficiency of any testing algorithm can be further improved in the presence of efficient algorithms for constructing the reference fault pattern. In this paper, we establish several new properties of catostrophic fault patterns: based on these properties, as well as the existing ones, we develop a new algorithm for the construction of the reference fault pattern. The complexity of the new algorithm is O( kg ) which is a significant improvement over the existing O( g 2 ) algorithm, where k is the number of bypass links, and g is the length of the largest bypass link.


Information Processing Letters | 1995

A note on isomorphic chordal rings

Amiya Nayak; Vincenzo Accia; Paolo Gissi

Abstract Let G be a chordal ring with n vertices. In this paper we prove that if the degree of G is less than Φ(n), where Φ denotes the ordinary Euler function of an integer, then there are at most n − 1 chordal rings isomorphic to G and for which the length of the longest link is bounded by Φ(n).


Integration | 1996

On testing for catastrophic faults in reconfigurable arrays with arbitrary link redundancy

Amiya Nayak; Linda Pagli; Nicola Santoro

Abstract Fault tolerance through the incorporation of redundancy and reconfiguration is quite common. The distribution of faults can have severe impact on the effectiveness of any reconfiguration scheme; in fact, patterns of faults occurring at strategic locations may render an entire system unusable regardless of its component redundancy and its reconfiguration capabilities. Testing of catastrophic faults was given for reconfigurable arrays with 2-link redundancy; i.e., a bypass link of fixed length is provided to each element of the array in addition to the regular link. In this paper, we study the more general case of arbitrary (but regular) link redundancy. In particular, we focus on the problem of deciding whether a pattern of k faults is catastrophic for a k-link redundant system; i.e., in addition to the regular link of length g 1 = 1, each element of the array is provided with k −1 bypass links of length g 2, g 3,… g k, respectively. We study this problem and prove some fundamental properties which any catastrophic fault pattern must satisfy. We then show that these properties together constitute a necessary and sufficient condition for a fault pattern to be catastrophic for a k-link redundant system. As a consequence, we derive a provably correct testing algorithm whose worst-case time complexity is O(k g k); this also improves on the previous algorithm for k = 2.


Information Processing Letters | 2000

An improved testing scheme for catastrophic fault patterns

Amiya Nayak; J. Ren; Nicola Santoro

In a linear array of processors, a single faulty element in any location is sufficient to stop the flow of information from one side to the other. A common approach for achieving fault tolerance in such systems is through the incorporation of redundant links in a regular fashion. These links (called bypass links ) can be activated in a reconfiguration phase to bypass faulty elements. There are some inherent limits in this approach. In particular, there are sets of faults occurring in strategic locations which affect the entire system in an unrepairable way, regardless of the amount of redundancy, and cannot be overcome by any clever reconfiguration process, see [7]. These sets of faults are calledCatastrophic Fault Patterns (CFP) and have been extensively studied in the literature [1,2,4–6,8, 10]. The rather intuitive guess that any cut set is a CFP is unfortunately incorrect; on the contrary, they have a rather interesting structure with non-trivial symmetries


Information Processing Letters | 2002

On enumeration of catastrophic fault patterns

Soumen Maity; Bimal K. Roy; Amiya Nayak

} has been done in [2] for bidirectional caseand in [9] for unidirectional case. A method of enu-meration of CFPs in the more general context is givenin [8], but no closed form solution has been obtained.In this paper, we consider only bidirectional case anduse random walk as a tool for such enumeration. Weprovideasimple proofforthecase


international parallel processing symposium | 1991

Bounds on performance of VLSI processor arrays

Amiya Nayak; Nicola Santoro

This paper discusses the effect of processor failures on computation performed on two-dimensional VLSI processor arrays. Previously established properties of catastrophic fault patterns are used to study inherent limits to reconfigurability of these regular architectures. Bounds on number of faults the system can tolerate to provide guaranteed performance are derived. These results are the generalization of the results obtained in the case of one-dimensional processor arrays.<<ETX>>


international symposium on algorithms and computation | 1995

On the Complexity of Testing for Catastrophic Faults

Nicola Santoro; J. Ren; Amiya Nayak

In this paper, the problem of determining a fault pattern to be catastrophic for unidirectional linear array with k- link redundancy is studied. First, we establish a necessary and sufficient condition for a fault pattern to be catastrophic. Based on this necessary and sufficient condition, we derive an efficient testing algorithm whose complexity is O(mk), where k is the number of bypass links, and m is the number of faults. This testing scheme, which improves the existing O(mk log k) bound, is based on a novel “geometric” approach.


international symposium on microarchitecture | 1990

A survey on bit dimension optimization strategies of microprograms

Sunil R. Das; Amiya Nayak

Microprogram optimization is one way to increase efficiency, and optimization can be crucial in some applications. Optimization refers to a reduction of execution time of microprograms, or of the control store size, B*W, where W represents the word dimension of the control store which is the number of words of control store required for certain application, and B represents the bit dimension which is the number of bits per word of control store. The various optimization strategies can be broadly classified under four categories: bit dimension reduction, word dimension reduction, state reduction, and heuristic reduction. A survey of the various bit dimension optimization techniques has been presented by Agerwala in his 1976 paper, where the techniques are critically analyzed and compared, and the results of analysis are discussed. The paper further augments the work of Agerwala, taking into account the optimization methods developed later and hence not discussed by him. Also, the present study considers the optimization problem in the case of polyphase microinstructions in addition to that for monophase microinstructions. The prospective, current status, and future trends in this direction are also briefly outlined.<<ETX>>


Integration | 2001

Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links

Soumen Maity; Bimal K. Roy; Amiya Nayak

Characterization of catastrophic fault patterns (CFPs) and their enumeration have been studied by several authors. Given a linear array with a set of bypass links, an important problem is how to count the number of CFPs. Enumeration of CFPs for two link redundancy G ¼f 1; gg has been solved for both unidirectional and bidirectional link cases. In this paper, we consider the more general case of link redundancy G ¼f 1; 2;y; k; gg; 2pkog: Using random walk as a tool, we enumerate CFPs for both unidirectional and bidirectional cases. r 2001 Elsevier Science B.V. All rights reserved.

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Mansour H. Assaf

University of the South Pacific

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J. Ren

Carleton University

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Bimal K. Roy

Indian Statistical Institute

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Soumen Maity

Indian Institute of Technology Guwahati

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