Amresh Kumar

Online banking adoption

Purpose – The study considers a five-factor model toward online banking adoption in the context of banking customers in India and validates the proposed model. In addition, the authors consider the impact of validated factors on overall satisfaction of customers. Design/methodology/approach – A five-factor online banking adoption model has been tested for reliability and validity by confirmatory factor analysis. For determining contribution of factors toward overall satisfaction level of banking customers structural equation modeling has been adopted. Four explanatory variables have been used to assess the overall satisfaction level of online banking users. A structured questionnaire incorporating variables identified from literature has been used as survey instrument for the study. Final respondent sample was 280 banking customers. Findings – Trust, Usage Constraint, Ease of Use, Accessibility and Intention to Use as reliable and valid factors determining internet banking adoption among customers in Indi...

Payment Bank: A Catalyst for Financial Inclusion:

The study investigates how newly licensed payment banks can favourably achieve inclusion goals of the Indian banking regulator by engaging with marginalised and migrant groups within the population pie, as envisaged by the banking regulator. The role of digitisation in making basic financial services available to such excluded groups has been explored within the study. In addition, the article attempts to critically assess the competitive implications such a new financial institution will have on the existing full-service banks. The study is grounded on the concept of payment banks as a crucial cog in a differentiated banking regime. Secondary information extracted from occasional reports/working papers of Reserve Bank of India (RBI) has been used to gauge the efforts towards realising inclusion goals. Perspectives of CEOs and banking practitioners have provided valuable inputs as to how the banking fraternity views payment banks and perceives them as a competitive threat. As the payment banking business model necessitates forging alliances with full-service banks, implications of such strategic alliances warrant research. The present study is an initial attempt to fill this gap in the extant literature.

Propagation delay and its robustness study of inverter topologies

This paper analyzes the delay and delay variability by realizing the inverter circuit in different logic families. Speed plays a major role in todays VLSI circuits and even a fraction of delay affects the circuits by a large factor. Variability, just like other factors such as delay, area and power has emerged to be a key factor in designing circuits. CMOS families comprises of both single-ended and differential type logic circuits. The outputs of the inverters are investigated at 32-nm technology node in HSPICE model. The logic family with least variability and delay are reported to aid the designer in selecting the best logic family as per the requirement.

Comparative analysis of D flip-flops in terms of delay and its variability

There is vast variation encountered in present circuits because of aggressive scaling and process imperfections. So this paper deals with various D flip-flop circuits in terms of robustness and propagation delay. This work compares various known D flip-flop circuits and then identifies the circuit which is fastest as compared to others taken into consideration. Further, delay variability exhibited by circuits has been analyzed to test the immunity against PVT variations i.e. process, voltage and temperature. In this paper, we have investigated the output levels of various D flip-flop circuits. Push-pull isolation D flip-flop proves to be more efficient as compared to other circuits in terms of delay variability. The circuits have been simulated using 32-nm technology node on SPICE. The designs offering minimum delay and its variability are reported, to aid the designer in selecting the best design depending on specific requirements.

Performance evaluation of CNFET based operational amplifier at technology node beyond 45-nm

Bulk CMOS technology is facing enormous challenges at channel lengths below 45 nm such as gate tunneling, device mismatch, random dopant fluctuations, mobility degradation, etc. Although multiple gate transistors and strained silicon devices overcome some of the bulk CMOS problems, it is sensible to look for revolutionary new materials and devices to replace silicon. It is obvious that future technology materials should exhibit higher mobility, better channel electrostatics, scalability, and robustness against process variations. Carbon nanotube based technology is very promising because it has most of these desired features. There is a need to explore the potential of this emerging technology by designing circuits based on this technology and comparing their performance with that of existing bulk CMOS technology for its rapid commercialization. Therefore, this paper presents a comparative study of CMOS version and CNFET version of Operational amplifier at 32-nm technology nodes. The performance of CNFET based amplifier has been thoroughly investigated in terms of its input resistance, output resistance and AC gain. This study shows that there is considerable improvement in the above feature of amplifier using CNFET. It is founded that CNFET based amplifier have 9 times AC gain, 100 times input résistance and output resistance decrease by 9 times compared to MOSFET based amplifier at 32-nm technology node. Furthermore, comparison between two technologies for same gain bandwidth product (GBP) has also been presented.