Ana L. Salas-Villasenor

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70°C) on either 100 nm HfO 2 or SiO 2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS-based thin film transistors shows a field effect mobility and threshold voltage of 25 cm 2 V -1 s -1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO 2 .

Low-Temperature Hybrid CMOS Circuits Based on Chalcogenides and Organic TFTs

In this letter, we demonstrate a fully integrated approach to fabricate cadmium sulfide (CdS)-pentacene complementary metal-oxide-semiconductor (CMOS) digital circuits compatible with flexible electronics. Low-cost and low-temperature chemical bath deposition is used to deposit CdS at 70°C with mobility values >; 10 cm2/V·s and threshold voltages around 5 V for fully integrated devices. p-MOS thin-film transistors were fabricated using thermally evaporated pentacene as semiconductor with mobility and threshold voltages in the range of 3×10-2 cm2/V·s and -3 V, respectively. The CMOS integration approach includes six mask levels with a maximum processing temperature of 100°C.

Fabrication and Characterization of High-Mobility Solution-Based Chalcogenide Thin-Film Transistors

We report device and material considerations for the fabrication of high-mobility thin-film transistors (TFTs) compatible with large-area and inexpensive processes. In particular, this paper reports photolithographically defined n-type TFTs (n-TFTs) based on cadmium sulfide (CdS) films deposited using solution-based techniques. The integration process consists of four mask levels with a maximum processing temperature of 100°C. The TFT performance was analyzed in terms of the CdS semiconductor thickness and as a function of postdeposition annealing in a reducing ambient. The Ion/Ioff ratios are ~107 with field-effect mobilities of ~5.3 and ~4.7 cm2/V · s for Al and Au source-drain contacts, respectively, using 70 nm of CdS. Transmission electron microscopy and electron energy loss spectroscopy were used to analyze the CdS-metal interfaces.

Performance and stability of solution-based cadmium sulfide thin film transistors: Role of CdS cluster size and film composition

Improved carrier mobility and threshold voltage (VT) stability in cadmium sulfide (CdS) thin film transistors (TFTs) were studied and attributed to larger grain clusters in thicker CdS films rather than individual crystallite size. Non-zero VT shifts (∼200 mV) in thicker films are attributed to the presence of cadmium hydroxide [Cd(OH)2] at the dielectric/CdS interface resulting from the chemical bath deposition process used to deposit the CdS films. VT and mobility analyses indicate that clusters of CdS grains have a larger impact on TFT performance and stability than the presence of impurities in the bulk of the CdS. TFTs using this fabrication method achieved mobilities of ∼22 cm2/Vs with VT of 7 V and ΔVT of <200 mV after testing. The maximum processing temperature is 100 °C which makes this process compatible with flexible substrates.

Improved electrical stability of CdS thin film transistors through hydrogen-based thermal treatments

Thin film transistors (TFTs) with a bottom-gate configuration were fabricated using a photolithography process with chemically bath deposited (CBD) cadmium sulfide (CdS) films as the active channel. Thermal annealing in hydrogen was used to improve electrical stability and performance of the resulting CdS TFTs. Hydrogen thermal treatments results in significant V T instability (V T shift) improvement while increasing the I on/I off ratio without degrading carrier mobility. It is demonstrated that after annealing V T shift and I on/I off improves from 10 V to 4.6 V and from 105 to 109, respectively. Carrier mobility remains in the order of 14.5 cm2 V s−1. The reduced V T shift and performance is attributed to a reduction in oxygen species in the CdS after hydrogen annealing, as evaluated by Fourier transform infrared spectroscopy (FTIR).

Enabling Hybrid Complementary-TFTs With Inkjet Printed TIPS-Pentacene and Chemical Bath Deposited CdS

We report the fabrication and device analysis to enable high performance/low-temperature complementary thin-film transistors (CTFTs) with 6, 13-Bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) and cadmium sulfide (CdS). Isolated transistors are first studied and then integrated in a fully patterned CTFT structure. N-type TFTs were fabricated using atomic layer deposition HfO2 as gate dielectric, followed by a CdS film deposited by chemical bath deposition at 70 °C. A novel approach that uses a parylene-C hard mask to avoid damage to the CdS n-type semiconductor is introduced. Also, a comparison between the n-type transistor performance using two different metals (Au and Al) for source-drain electrodes is presented. P-type transistors were fabricated using a novel approach that combines photolithography and ink-jet printing processes. TIPS-pentacene is deposited with inkjet printing in the active channel well, which is photolithographically defined. The p-type TFT mobilities ranged from 1.2×10-3 to 1.5×10-2 cm2/V-s, whereas for n-type TFTs mobilities were ~ 10 cm2/V-s. CTFTs with a maximum processing temperature of 150 °C are demonstrated. Inverters with gains of 17 were achieved. This fabrication process is compatible with large area and low-cost technologies for flexible electronics applications.

Electrical stress in CdS thin film transistors using HfO2 gate dielectric

During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, Ion/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve.

Modeling and SPICE simulation of CdS-pentacene hybrid CMOS TFTs

In this work we demonstrate that the unified model and parameter extraction method (UMEM) can be used to describe the behavior of hybrid complementary metal-oxide-semiconductor thin film transistors (CMOS TFTs) fabricated with cadmium sulfide (CdS) and pentacene as n-type and p-type active layer, respectively. Both devices were fabricated using a bottom gate configuration and top source-drain (SD) contacts. In particular, we describe the effect of semiconductor defects using the effective medium approximation, which considers a localized charge distribution in the bandgap of the semiconductor. Extracted parameters from UMEM were used in HSPICE to simulate the CMOS inverters fabricated previously by our group.

Indicators of mobility extraction error in bottom gate CdS metal-oxide-semiconductor field-effect transistors

Widely varying mobility values of CdS metal-oxide-semiconductor field-effect transistors have been reported in the literature (μ = 1–48 cm2/Vs). Sulfide vacancies in CdS channel generated by an incomplete post deposition anneal are found to be the origin of scattered mobility values. The presence of sulfide vacancies can be easily diagnosed by simple electrical measurements checking a strong channel length dependence of mobility and an abrupt drain current increase due to the carrier ionization at sulfur vacancies.

Solution-Based CdS on HfO 2 Thin Films for High-Gain and Low-Voltage Unipolar Inverters

We demonstrate low-temperature processed and high-gain unipolar inverters operating at voltages as low as VD = 1 V. A maximum gain for a two-transistor unipolar inverter of 153 was achieved at VD = 5 V with the advantage of using a solution-based n-type semiconductor and an entire fabrication process below 150 °C. We evaluate the impact of the gate dielectric thickness on the main thin-film transistor (TFT) parameters and operation voltage. In addition, we compare the conventional MOSFET square-law model indistinctly used in TFTs with a model specifically developed for TFTs. We demonstrate a methodology to model the TFT electrical characteristics and use the extracted parameters in SPICE simulations to evaluate different inverter configurations. Finally, we validate the SPICE simulations with our experiential results.