M. A. Quevedo-Lopez

Dipole model explaining high-k/metal gate field effect transistor threshold voltage tuning

An interface dipole model explaining threshold voltage (Vt) tuning in HfSiON gated n-channel field effect transistors (nFETs) is proposed. Vt tuning depends on rare earth (RE) type and diffusion in Si∕SiOx∕HfSiON∕REOx/metal gated nFETs as follows: Sr<Er<Sc+Er<La<Sc<none. This Vt ordering is very similar to the trends in dopant electronegativity (EN) (dipole charge transfer) and ionic radius (r) (dipole separation) expected for a interfacial dipole mechanism. The resulting Vt dependence on RE dopant allows distinction between a dipole model (dependent on EN and r) and an oxygen vacancy model (dependent on valence).

Nucleation and growth study of atomic layer deposited HfO2 gate dielectrics resulting in improved scaling and electron mobility

HfO2 films have been grown with two atomic layer deposition (ALD) chemistries: (a) tetrakis(ethylmethylamino)hafnium (TEMAHf)+O3 and (b) HfCl4+H2O. The resulting films were studied as a function of ALD cycle number on Si(100) surfaces prepared with chemical oxide, HF last, and NH3 annealing. TEMAHf+O3 growth is independent of surface preparation, while HfCl4+H2O shows a surface dependence. Rutherford backscattering shows that HfCl4+H2O coverage per cycle is l3% of a monolayer on chemical oxide while TEMAHf+O3 coverage per cycle is 23% of a monolayer independent of surface. Low energy ion scattering, x-ray reflectivity, and x-ray photoelectron spectroscopy were used to understand film continuity, density, and chemical bonding. TEMAHf+O3 ALD shows continuous films, density >9g∕cm3, and bulk Hf–O bonding after 15 cycles [physical thickness (Tphys)=1.2±0.2nm] even on H-terminated Si(100). Conversely, on H-terminated Si(100), HfCl4+H2O requires 50 cycles (Tphys∼3nm) for continuous films and bulk Hf–O bonding. ...

Work function engineering using lanthanum oxide interfacial layers

A La2O3 capping scheme has been developed to obtain n-type band-edge metal gates on Hf-based gate dielectrics. The viability of the technique is demonstrated using multiple metal gates that normally show midgap work function when deposited directly on HfSiO. The technique involves depositing a thin interfacial of La2O3 on a Hf-based gate dielectric prior to metal gate deposition. This process preserves the excellent device characteristic of Hf-based dielectrics, but also allows the realization of band-edge metal gates. The effectiveness of the technique is demonstrated by fabricating fully functional transistor devices. A model is proposed to explain the effect of La2O3 capping on metal gate work function.

Metal gate work function engineering using AlNx interfacial layers

Metal gate work function enhancement using thin AlNx interfacial layers has been evaluated. It was found that band edge effective work functions (∼5.10eV) can be achieved on hafnium-based high dielectric constant (high-k) materials using the AlNx interfacial layer and TiSiN electrodes. It was also found that the effective work function enhancement by the AlNx interfacial layer increased when the concentration of SiO2 in the gate dielectric was increased. Thus, the enhancement was minimal for HfO2 and maximum for SiO2. A model is proposed to explain these results and a bonding analysis is presented to support the proposed model.

Comparison of electrical and chemical characteristics of ultrathin HfON versus HfSiON dielectrics

The electrical and chemical properties of ultrathin HfON and HfSiON gate dielectrics are investigated as a function of physical thickness. Grazing incidence x-ray diffraction was used to detect phase separation and crystallization of 1.5, 2.0, 2.5, and 4.0nm films of HfON and HfSiON after a 1000°C-10s activation annealing. X-ray photoelectron spectroscopy was used to determine the chemical composition of the dielectrics. No evidence of crystallization was detected in 1.5nm HfON or HfSiON films after the activation annealing. The HfON film showed crystallization at a 2.0nm thickness whereas the 2.0nm HfSiON film remained amorphous.

Effect of thickness on the crystallization of ultrathin HfSiON gate dielectrics

The crystallization of ultrathin hafnium silicon oxynitride (HfSiON) gate dielectric is studied as a function of physical thickness. Grazing incidence x-ray diffraction (GI-XRD) was used to detect phase separation and crystallization of 1.5, 2.0, 2.5, and 4.0 nm HfSiON films after 1000°C10s dopant activation anneal. Crystallization peaks corresponding to monoclinic and tetragonal HfO2 were detected in 2.5 and 4.0 nm HfSiON films. These GI-XRD results were supported by plan-view transmission electron microscopy images of the HfSiON films. Film crystallinity seems to impact voltage instability in thicker HfSiON films.

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70°C) on either 100 nm HfO 2 or SiO 2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS-based thin film transistors shows a field effect mobility and threshold voltage of 25 cm 2 V -1 s -1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO 2 .

Mobility and charge trapping comparison for crystalline and amorphous HfON and HfSiON gate dielectrics

Mobility and charge trapping results for n-channel transistors gated with HfON and HfSiON are reported as a function of physical thickness (Tphys). HfSiON peak mobility improves with Tphys over the range of 1.8–2.7nm, achieving 260cm2∕Vs at 2.7nm. However, HfSiON mobility degrades at a critical thickness, Tphys⩾3.5nm. HfON mobility response is different. It is a maximum (230cm2∕Vs) at Tphys=1.2nm but degrades with increasing thickness, particularly for the critical thickness ⩾2.5nm. Mobility loss and trapping occur concurrently for both dielectrics when these critical thicknesses are exceeded. These critical thicknesses are the minimum required to achieve dielectric crystallization. Interfacial defects along crystalline grain boundaries may negatively impact electrical performance of both dielectrics.

Mobility enhancement of high-k gate stacks through reduced transient charging

We report a high performance NFET with a HfO/sub 2//TiN gate stack showing high field (1 MV/cm) DC mobility of 194 cm/sup 2//V-s (80% univ. SiO/sub 2/) and peak DC mobility of 239 cm/sup 2//V-s at EOT=9.5/spl Aring/. These mobility results are among the best reported for HfO/sub 2/ with sub-10 /spl Aring/ EOT and represent a potential gate dielectric solution for 45 nm CMOS technologies. A 2/spl times/ mobility improvement was realized by thinning HfO/sub 2/ from T/sub phys/=4.0 nm to 2.0 nm. The mechanism for mobility improvement is shown to be reduced transient charge trapping. Issues associated with scaling HfO/sub 2/ including film continuity, density and growth incubation are studied with low energy ion scattering (LEIS), X-ray reflectivity (XRR) and Rutherford backscattering (RBS) and indicate atomic layer deposition (ALD) HfO/sub 2/ can scale below T/sub phys/= 2.0 nm. While the mobility advancement with 2.0 nm HfO/sub 2/ is important, an additional concurrent advancement is improved V/sub t/ stability. Constant voltage stress results show /spl Delta/V/sub t/ improves 2/spl times/ after 1000s stress at 1.8V as thickness is reduced in the range 2.0-4.0 nm.

Co-optimization of the metal gate/high-k stack to achieve high-field mobility >90% of SiO/sub 2/ universal mobility with an EOT=/spl sim/1 nm

HfO/sub 2/ and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO/sub 2/ universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-/spl kappa/ dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO/sub 2/ and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO/sub 2/ gate stack.