Israel Mejia

Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70°C) on either 100 nm HfO 2 or SiO 2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS-based thin film transistors shows a field effect mobility and threshold voltage of 25 cm 2 V -1 s -1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO 2 .

Polarization behavior of poly"vinylidene fluoride-trifluoroethylene… copolymer ferroelectric thin film capacitors for nonvolatile memory application in flexible electronics

The time domain and electric field dependence of the polarization switching kinetics of poly(vinylidene fluoride-trifluoroethylene) copolymer based thin film metal-ferroelectric-metal capacitors have been characterized. At room temperature, the time required for complete switching polarization decreases from >1 s to <50 μs as the voltage is increased from 6 to 12 V, while low nonswitching polarization is maintained. In the time domain, the ferroelectric switching polarization reversal behavior for devices biased above the coercive field follows the nucleation-limited-switching model. The exponential relationship between switching time and applied electric field indicates nucleation dominated switching kinetics. Switching behavior as a function of temperature was also characterized from −60 to 100 °C in the voltage range of 6–12 V. Higher temperatures induce larger dc conductance leakage at low frequencies and increases nonswitching polarization for all the voltages studied. It is demonstrated that for cer...

Low-Temperature Hybrid CMOS Circuits Based on Chalcogenides and Organic TFTs

In this letter, we demonstrate a fully integrated approach to fabricate cadmium sulfide (CdS)-pentacene complementary metal-oxide-semiconductor (CMOS) digital circuits compatible with flexible electronics. Low-cost and low-temperature chemical bath deposition is used to deposit CdS at 70°C with mobility values >; 10 cm2/V·s and threshold voltages around 5 V for fully integrated devices. p-MOS thin-film transistors were fabricated using thermally evaporated pentacene as semiconductor with mobility and threshold voltages in the range of 3×10-2 cm2/V·s and -3 V, respectively. The CMOS integration approach includes six mask levels with a maximum processing temperature of 100°C.

Fabrication and Characterization of High-Mobility Solution-Based Chalcogenide Thin-Film Transistors

We report device and material considerations for the fabrication of high-mobility thin-film transistors (TFTs) compatible with large-area and inexpensive processes. In particular, this paper reports photolithographically defined n-type TFTs (n-TFTs) based on cadmium sulfide (CdS) films deposited using solution-based techniques. The integration process consists of four mask levels with a maximum processing temperature of 100°C. The TFT performance was analyzed in terms of the CdS semiconductor thickness and as a function of postdeposition annealing in a reducing ambient. The Ion/Ioff ratios are ~107 with field-effect mobilities of ~5.3 and ~4.7 cm2/V · s for Al and Au source-drain contacts, respectively, using 70 nm of CdS. Transmission electron microscopy and electron energy loss spectroscopy were used to analyze the CdS-metal interfaces.

Optimizing diode thickness for thin-film solid state thermal neutron detectors

In this work, we investigate the optimal thickness of a semiconductor diode for thin-film solid state thermal neutron detectors. We evaluate several diode materials, Si, CdTe, GaAs, C (diamond), and ZnO, and two neutron converter materials, 10B and 6LiF. Investigating a coplanar diode/converter geometry, we determine the minimum semiconductor thickness needed to achieve maximum neutron detection efficiency. By keeping the semiconductor thickness to a minimum, gamma rejection is kept as high as possible. In this way, we optimize detector performance for different thin-film semiconductor materials.

Performance and stability of solution-based cadmium sulfide thin film transistors: Role of CdS cluster size and film composition

Improved carrier mobility and threshold voltage (VT) stability in cadmium sulfide (CdS) thin film transistors (TFTs) were studied and attributed to larger grain clusters in thicker CdS films rather than individual crystallite size. Non-zero VT shifts (∼200 mV) in thicker films are attributed to the presence of cadmium hydroxide [Cd(OH)2] at the dielectric/CdS interface resulting from the chemical bath deposition process used to deposit the CdS films. VT and mobility analyses indicate that clusters of CdS grains have a larger impact on TFT performance and stability than the presence of impurities in the bulk of the CdS. TFTs using this fabrication method achieved mobilities of ∼22 cm2/Vs with VT of 7 V and ΔVT of <200 mV after testing. The maximum processing temperature is 100 °C which makes this process compatible with flexible substrates.

Low-temperature processed ZnO and CdS photodetectors deposited by pulsed laser deposition

UV-VIS photodetectors using an interdigital configuration, with zinc oxide (ZnO) and cadmium sulfide (CdS) semiconductors deposited by pulsed laser deposition, were fabricated with a maximum processing temperature of 100 °C. Without any further post-growth annealing, the photodetectors are compatible with flexible and transparent substrates. Aluminum (Al) and indium tin oxide (ITO) were investigated as contacts. Focusing on underwater communications, the impact of metal contact (ITO versus Al) was investigated to determine the maximum responsivity using a laser with a 405 nm wavelength. As expected, the responsivity increases for reduced metal finger separation. This is a consequence of reduced carrier transit time for shorter finger separation. For ITO, the highest responsivities for both films (ZnO and CdS) were ~3 A W−1 at 5 V. On the other hand, for Al contacts, the maximum responsivities at 5 V were ~0.1 A W−1 and 0.7 A W−1 for CdS and ZnO, respectively.

Thin film cadmium telluride charged particle sensors for large area neutron detectors

Thin film semiconductor neutron detectors are an attractive candidate to replace 3He neutron detectors, due to the possibility of low cost manufacturing and the potential for large areas. Polycrystalline CdTe is found to be an excellent material for thin film charged particle detectors—an integral component of a thin film neutron detector. The devices presented here are characterized in terms of their response to alpha and gamma radiation. Individual alpha particles are detected with an intrinsic efficiency of >80%, while the devices are largely insensitive to gamma rays, which is desirable so that the detector does not give false positive counts from gamma rays. The capacitance-voltage behavior of the devices is studied and correlated to the response due to alpha radiation. When coupled with a boron-based neutron converting material, the CdTe detectors are capable of detecting thermal neutrons.

Evaluation of (E)-1,2-di(furan-2-yl)ethene as building unit in diketopyrrolopyrrole alternating copolymers for transistors

Alternating copolymers, poly(2,5-bis(2-decyltetradecyl)-3,6-di(furan-2-yl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione-b-(E)-1,2-di(furan-2-yl)ethene) (P(FDPP-FVF)) and poly(2,5-bis(2-decyltetradecyl)-3,6-di(thiophen-2-yl)pyrrolo[3,4-c]pyrrole-1,4(2H,5H)-dione-b-(E)-1,2-di(furan-2-yl)ethene) (P(ThDPP-FVF)), composed of (E)-1,2-di(furan-2-yl)ethene and diketopyrrolopyrrole, were synthesized and studied for solution-processable organic field effect transistors (OFETs). Highest hole mobilities of 0.45 and 0.24 cm2 V−1 s−1 were measured for P(FDPP-FVF) and P(ThDPP-FVF), respectively, in bottom gate-bottom contact transistor devices. Atomic force microscopy and grazing incidence X-ray diffraction experiments were employed to investigate the crystallinity and morphology for the spin-cast polymer films. It is noteworthy that the thermally annealed P(FDPP-FVF) film exhibited higher crystallinity and small π-stacking distance of 3.47 A. Moreover, considering the easy synthesis from renewable furfural and better performance of P(FDPP-FVF), our results provide an alternative design strategy for the synthesis of solution-based semiconducting polymers from renewable furan derivatives for OFETs.

Sol–Gel PMMA–ZrO2 Hybrid Layers as Gate Dielectric for Low-Temperature ZnO-Based Thin-Film Transistors

We report a simple sol–gel process for the deposition of poly(methyl methacrylate) (PMMA)–ZrO2 organic–inorganic hybrid films at low temperature and studied their properties as a function of the molar ratios of the precursors in the hybrid sol–gel solution, which included zirconium propoxide as the inorganic (zirconia) source, methyl methacrylate as the organic source, and 3-trimethoxy-silyl-propyl-methacrylate (TMSPM) as the coupling agent to enhance the compatibility between the organic and inorganic phases. The hybrid thin-film deposition was done on glass slide substrates by the dip-coating method. After deposition, the films were heat-treated at 100 °C for 24 h. The analysis of the hybrid films included Fourier transform infrared spectroscopy to identify their chemical groups and thermogravimetric analysis to determine the content of their organic and inorganic components. In addition, capacitance–voltage (C–V) and current–voltage (I–V) curves in metal–insulator–metal structures, using gold as metal contacts, were measured to find the dielectric constant and leakage current of the PMMA–ZrO2 hybrid films. Finally, because of their adequate dielectric characteristics, single hybrid layers were deposited on indium tin oxide-coated glass substrates and were tested as gate dielectric in thin-film transistors (TFTs), using sputtered ZnO layers as the semiconductor active channel. We measured the output electrical response and transfer characteristics of these hybrid dielectric gate-based devices and determined their main electrical parameters as a function of the TMSPM content in the hybrid dielectric gate layer. The better TFT electrical behavior presents field effect mobility of 0.48 cm2/V s, low threshold voltage of 3.3 V, and on/off current ratio of 105, and it was obtained by using PMMA–ZrO2 with 0.3 TMSPM content as the gate dielectric layer. The values obtained for the electrical parameters show that PMMA–ZrO2 hybrid films are quite suitable for dielectric gate applications in TFTs