Anand Ganti

Base station assignment and power control algorithms for data users in a wireless multiaccess framework

This paper considers the problem of assigning mobile data users to base stations and modulating their transmit powers according to their respective channel gains in order to maximize the total system throughput. We consider two scenarios of time-invariant and time-varying channel behaviors. We show that the base station assignment problem is NP complete and propose sub-optimal polynomial time algorithms and bound their performance. When the channel gains are time-varying, we present an iterative algorithm to compute the assignment and power control functions according to the probability distribution of the channel gains. This algorithm is shown to converge to the optimal allocation in the special cases of a single user or a single base station. Simulation results demonstrate the performance of our algorithms, which are especially significant under asymmetric loading of the network

Brief announcement: the impact of classical electronics constraints on a solid-state logical qubit memory

We present and analyze an architecture for a logical qubit memory that is tolerant of faults in the processing of silicon double quantum dot (DQD) qubits. A highlight of our analysis is an in-depth consideration of the constraints faced when integrating DQDs with classical control electronics.

Family of[[6k,2k,2]]codes for practical and scalable adiabatic quantum computation

In this work, we introduce a new family of [[6k, 2k, 2]] codes designed specifically to be compatible with adiabatic quantum computation. These codes support computationally universal sets of weight-two logical operators and are particularly well-suited for implementing dynamical decoupling error suppression. For Hamiltonians embeddable on a planar graph of fixed degree, our encoding maintains a planar connectivity graph and increase the graph degree by only two. These codes are the first known to possess these features.

Implications of electronics constraints for solid-state quantum error correction and quantum circuit failure probability

In this paper we present the impact of classical electronics constraints on a solid-state quantum dot logical qubit architecture. Constraints due to routing density, bandwidth allocation, signal timing and thermally aware placement of classical supporting electronics significantly affect the quantum error correction circuits error rate (by a factor of ~3–4 in our specific analysis). We analyze one level of a quantum error correction circuit using nine data qubits in a Bacon–Shor code configured as a quantum memory. A hypothetical silicon double quantum dot quantum bit (qubit) is used as the fundamental element. A pessimistic estimate of the error probability of the quantum circuit is calculated using the total number of gates and idle time using a provably optimal schedule for the circuit operations obtained with an integer program methodology. The micro-architecture analysis provides insight about the different ways the electronics impact the circuit performance (e.g. extra idle time in the schedule), which can significantly limit the ultimate performance of any quantum circuit and therefore is a critical foundation for any future larger scale architecture analysis.