Thomas M. Gurrieri

Efficient clocked electron transfer on superfluid helium.

Unprecedented transport efficiency is demonstrated for electrons on the surface of micron-scale superfluid helium-filled channels by co-opting silicon processing technology to construct the equivalent of a charge-coupled device. Strong fringing fields lead to undetectably rare transfer failures after over a billion cycles in two dimensions. This extremely efficient transport is measured in 120 channels simultaneously with packets of up to 20 electrons, and down to singly occupied pixels. These results point the way towards the large scale transport of either computational qubits or electron spin qubits used for communications in a hybrid qubit system.

An Embeddable SOI Radiation Sensor

The feasibility of developing an embeddable silicon-on-insulator (SOI) buried oxide MOS dosimeter (RadFET) has been demonstrated. This dosimeter takes advantage of the inherent properties for radiation-induced charge buildup in the buried oxides of commercial SOI wafers. Discrete SOI buried oxide RadFETs and fully-functional read-out circuitry have been fabricated in Sandias CMOS7 radiation-hardened SOI technology. Discrete RadFETs have been irradiated under various radiation conditions and subjected to post-irradiation anneals. Data show only a small dose rate dependence and less than a 10% annealing or fade of the dosimeters output characteristics when irradiated with all pins shorted. These results show less fade than dual-dielectric RadFETs irradiated under the same bias conditions and support the use of SOI buried oxide RadFETs for low dose rate applications. Read-out circuitry has also been designed and fabricated to monitor changes in the ¿off¿ state leakage current induced by radiation-induced charge buildup in the buried oxide dosimeter. The analog-to-digital output from the read-out circuit changes linearly with the ¿off¿ state leakage current. Preliminary radiation characterizations of the read-out circuitry show no spurious effects of radiation-induced charge buildup in the read-out circuitry on the dosimeter output. These results indicate it is feasible to develop an embeddable SOI buried oxide RadFET as an attractive choice for many low power, low dose rate applications requiring real-time knowledge of total ionizing dose radiation levels.

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

Brief announcement: the impact of classical electronics constraints on a solid-state logical qubit memory

We present and analyze an architecture for a logical qubit memory that is tolerant of faults in the processing of silicon double quantum dot (DQD) qubits. A highlight of our analysis is an in-depth consideration of the constraints faced when integrating DQDs with classical control electronics.

Implications of electronics constraints for solid-state quantum error correction and quantum circuit failure probability

In this paper we present the impact of classical electronics constraints on a solid-state quantum dot logical qubit architecture. Constraints due to routing density, bandwidth allocation, signal timing and thermally aware placement of classical supporting electronics significantly affect the quantum error correction circuits error rate (by a factor of ~3–4 in our specific analysis). We analyze one level of a quantum error correction circuit using nine data qubits in a Bacon–Shor code configured as a quantum memory. A hypothetical silicon double quantum dot quantum bit (qubit) is used as the fundamental element. A pessimistic estimate of the error probability of the quantum circuit is calculated using the total number of gates and idle time using a provably optimal schedule for the circuit operations obtained with an integer program methodology. The micro-architecture analysis provides insight about the different ways the electronics impact the circuit performance (e.g. extra idle time in the schedule), which can significantly limit the ultimate performance of any quantum circuit and therefore is a critical foundation for any future larger scale architecture analysis.

Spatial distribution of electrons on a superfluid helium charge-coupled device

Electrons floating on the surface of superfluid helium have been suggested as promising mobile spin qubits. Three micron wide channels fabricated with standard silicon processing are filled with superfluid helium by capillary action. Photoemitted electrons are held by voltages applied to underlying gates. The gates are connected as a 3-phase charge-coupled device (CCD). Starting with approximately one electron per channel, no detectable transfer errors occur while clocking 109 pixels. One channel with its associated gates is perpendicular to the other 120, providing a CCD which can transfer electrons between the others. This perpendicular channel has not only shown efficient electron transport but also serves as a way to measure the uniformity of the electron occupancy in the 120 parallel channels.