James E. Levy

Coherent Electron Transport by Adiabatic Passage in an Imperfect Donor Chain

Coherent tunneling adiabatic passage (CTAP) has been proposed as a long-range physical quantum bits (qubit) transport mechanism in solid-state quantum computing architectures. Although the mechanism can be implemented in either a chain of quantum dots or donors, a one-dimensional chain of donors in Si is of particular interest due to the natural confining potential of donors that can, in principle, help reduce the gate densities in solid-state quantum computing architectures. Using detailed atomistic modeling, we investigate CTAP in a more realistic triple donor system in the presence of inevitable fabrication imperfections. In particular, we investigate how an adiabatic pathway for CTAP is affected by donor misplacements and propose schemes to correct for such errors. We also investigate the sensitivity of the adiabatic path to gate voltage fluctuations. The tight-binding based atomistic treatment of straggle used here may benefit understanding of other donor nanostructures, such as donor-based charge and spin qubits. Finally, we derive an effective 3×3 model of CTAP that accurately resembles the voltage tuned lowest energy states of the multimillion atom tight-binding simulations and provides a translation between intensive atomistic Hamiltonians and simplified effective Hamiltonians while retaining the relevant atomic-scale information. This method can help characterize multidonor experimental structures quickly and accurately even in the presence of imperfections, overcoming some of the numeric intractabilities of finding optimal eigenstates for nonideal donor placements

CMOS Integrated Single Electron Transistor Electrometry (CMOS-SET) Circuit Design for Nanosecond Quantum-Bit Read-out

Novel single electron transistor (SET) read-out circuit designs are described. The circuits use a silicon SET interfaced to a CMOS voltage mode or current mode comparator to obtain a digital read-out of the state of the qubit. The design assumes standard submicron (0.35 um) CMOS SOI technology using room temperature SPICE models. Implications and uncertainties related to the temperature scaling of these models to 100mK operation are discussed. Using this technology, the simulations predict a read-out operation speed of approximately Ins and a power dissipation per cell as low as 2nW for single-shot read-out, which is a significant advantage over currently used radio frequency SET (RF-SET) approaches.

Brief announcement: the impact of classical electronics constraints on a solid-state logical qubit memory

We present and analyze an architecture for a logical qubit memory that is tolerant of faults in the processing of silicon double quantum dot (DQD) qubits. A highlight of our analysis is an in-depth consideration of the constraints faced when integrating DQDs with classical control electronics.

Implications of electronics constraints for solid-state quantum error correction and quantum circuit failure probability

In this paper we present the impact of classical electronics constraints on a solid-state quantum dot logical qubit architecture. Constraints due to routing density, bandwidth allocation, signal timing and thermally aware placement of classical supporting electronics significantly affect the quantum error correction circuits error rate (by a factor of ~3–4 in our specific analysis). We analyze one level of a quantum error correction circuit using nine data qubits in a Bacon–Shor code configured as a quantum memory. A hypothetical silicon double quantum dot quantum bit (qubit) is used as the fundamental element. A pessimistic estimate of the error probability of the quantum circuit is calculated using the total number of gates and idle time using a provably optimal schedule for the circuit operations obtained with an integer program methodology. The micro-architecture analysis provides insight about the different ways the electronics impact the circuit performance (e.g. extra idle time in the schedule), which can significantly limit the ultimate performance of any quantum circuit and therefore is a critical foundation for any future larger scale architecture analysis.

Capacitance Modeling of Complex Topographical Silicon Quantum Dot Structures

Quantum dot (QD) layouts are becoming more complex as the technology is being applied to more sophisticated multi-QD structures. This increase in complexity requires improved capacitance modeling both for the design and accurate interpretation of QD properties from measurement. A combination of process simulation, electrostatic simulation, and computer-assisted design (CAD) layout packages are used to develop a 3-D classical capacitance model. The agreement of the classical models capacitances is tested against two different, experimentally measured, topographically complex silicon QD geometries. Agreement with experiment, within 10%-20%, is demonstrated for the two structures when the details of the structure are transferred from the CAD to the model capturing the full 3-D topography. Small uncertainties in device dimensions due to uncontrolled variation in processing, like layer thickness and gate size, are calculated to be sufficient to explain the disagreement. The sensitivity of the capacitances to small variations in the structure also highlights the limits of accuracy of capacitance models for QD analysis. We furthermore observe that a critical density, the metal-insulator transition, can be used as a good approximation of the metallic edge of the QD when electron density in the dot is calculated directly with a semiclassical simulation.

Front-side mid-level Tungsten TSV integration for high-density 3D applications

We demonstrate a front-side process integration method to insert high-density 1.2um diameter Tungsten (W) Through Silicon Vias (TSVs) into advanced-node logic wafers after metal-4. This late-TSV-middle approach offers the ability to build 3D technology into commercially available 90nm-node CMOS, while avoiding many of the challenges associated with TSV-last integrations. We also demonstrate a TSV-reveal process compatible with small-diameter W TSVs.