Anand Savanth

8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications

The Internet of Things is widely expected to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). One challenge this poses is energy efficiency, as it will prove cost-prohibitive to regularly replace billions of batteries. Node cost is another concern, which will demand ever-greater integration. Ease of SW development must also remain a priority to HW designers. Addressing all of the above, this paper presents an 11.7pJ/cycle subthreshold WSN processing sub-system implemented in low-leakage 65nm CMOS, scalable from 850nW active power at 250mV to 66MHz at 900mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80nW CPU and RAM state-retention power gating for SW-transparent leakage reduction.

A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator

The Internet of Things (IoT) is widely predicted to comprise billions of connected devices, many of which will be wireless sensor nodes (WSN). Energy efficiency is a huge challenge here, followed by node cost and ease of software (SW) development. Addressing all of the above, this paper presents an 11.7 pJ/cycle subthreshold ARM Cortex-M0+ WSN processing subsystem implemented in low-leakage 65 nm CMOS. Voltage and frequency scalability is from 850 nW active power at 250 mV to 66 MHz above 900 mV, with a fully integrated 82% peak-efficiency voltage regulator for direct-battery operation, and supporting 80 nW CPU and RAM state-retention power gating for SW transparent leakage reduction. SW and system optimization approaches are described and a 2.94 μW SW ECG workload is presented.

Photovoltaic Cells for Micro-Scale Wireless Sensor Nodes: Measurement and Modeling to Assist System Design

Energy harvesting enables perpetual operation of wireless sensor nodes by scavenging energy from the environment. Light energy harvesting using photovoltaic (PV) cells is preferred as they offer the highest volumetric power output allowing nodes to be as small as possible. However, their power output can be spatially and temporally-variable. This work investigates the performance of cm2-scale photovoltaic (PV) cells, and reports on a new measurement and characterization platform. Results show that micro photovoltaic (PV) cells perform differently from large panels: power is not simply a function of area and light levels, and manufacturing variability can be a major issue. The method presented enables the rational design of micro-scale systems, including their maximum power point tracking circuits, and the evaluation of techniques for energy-neutrality (such as workload throttling) at design-time.

Energy Neutral Sensor System With Micro-scale Photovoltaic and Thermoelectric Energy Harvesting

Minimizing power conversion losses is critical for energy neutral operation of micro-scale energy harvested sensor nodes. These small form-factor sensor nodes rely on miniature harvesters with low output voltages that must be boosted with large conversion ratios to recharge batteries or super-capacitors. Selective Direct Operation (SDO), a technique to selectively avoid power conversion and thereby eliminate conversion loss in energy harvested systems has been demonstrated as an effective technique for light harvesters. This paper extends SDO to thermoelectric generators (TEGs). SDO exploits the ultra-low circuit functional voltages, enabling sensor systems to effectively harvest energy from cm-scale TEGs which output few 10s of mW but at low output voltages (100s of mV). PV cell construction from prior-work, TEG characterization and field measurements are presented in this paper to demonstrate the effectiveness of SDO and co-designing energy harvesters, power conversion circuits and digital sub-systems.

Integrated Reciprocal Conversion With Selective Direct Operation for Energy Harvesting Systems

Energy harvesting IoT systems aim for energy neutrality, i.e., harvesting at least as much energy as is needed. This, however, is complicated by variations in environmental energy and application demands. Conventional systems use separate power converters to interface between the harvester and the storage, and then to the CPU system. Reciprocal power conversion has recently been proposed to perform both roles, eliminating redundancy and minimizing losses. This paper proposes to enhance this topology with “selective direct operation,” which completely bypasses the converter when appropriate. The integrated system, with 82% bidirectional conversion efficiency, was validated in 65-nm CMOS with only the harvester, battery, and decoupling capacitors being off-chip. Optimized for operation with cm2 photo-voltaic cell and a 32-b sub-threshold processor, the scheme enables up to 16% otherwise wasted energy to be utilized to provide >30% additional compute cycles under realistic indoor lighting conditions. Measured results show 84% peak conversion efficiency and energy neutral execution of benchmark sensor software (ULPBench) with cold-start capability.

Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem

Energy-efficient, low-cost wireless sensor nodes (WSN) will be a key component in enabling the Internet of Things. The main challenges for these nodes are energy efficiency, cost and ease of software development. At ARM Research, we investigate sub-threshold and near-threshold systems using a custom-built 65nm CMOS ARM Cortex-M0+ platform. This paper will present key challenges of implementing an ultra-low-voltage SoC, managing leakage and dynamic power, and scaling operating voltage from full voltage to sub-threshold operation. We will cover the design of custom voltage regulator and SRAM IP blocks and also consider a real-world ECG signal processing application.

A 12.4pJ/cycle sub-threshold, 16pJ/cycle near-threshold ARM Cortex-M0+ MCU with autonomous SRPG/DVFS and temperature tracking clocks

IoT requirements are almost as varied as the Things to which they are applied, but common demands are maximum battery life with minimum system cost and physical volume. Sub-threshold operation is promising, but even a single un-optimized or always-on component can eliminate low-voltage gains elsewhere. This work presents a highly integrated sub-threshold capable ARM based MCU with fully integrated multi-mode IVR, always-on power control, and on-chip clock sources, achieving 12.44pJ/cycle active energy (6.3pJ/cycle ideal), 139.4nW standby power (46nW ideal) and 1μW ULPBench power. Simple adaptive circuits are demonstrated to be efficient and correct for standby IVR and active system clocks across 0–70°C.

Evaluation and analysis of single-phase clock flip-flops for NTV applications

Performance slack in IoT applications is routinely exploited in sensor nodes to minimize power by aggressive voltage scaling. However, scaling voltage to sub-threshold levels causes severe degradation in performance and is prone to On Chip Variation (OCV). In contrast, Near Threshold Voltage (NTV) operation offers a good balance between performance loss, OCV and energy reduction and is promising for industry adoption. Unlike sub-threshold operation, where leakage power dominates, NTV designs benefit from dynamic power saving techniques, such as Single-Phase Clocked Flip-Flops (SPC FFs), which eliminate internal clock buffers. In this context, this work reviews prominent types of state-of-the-art SPC FFs and analyses their suitability for NTV operation. Five SPC FFs are reviewed and based on a preliminary analysis, two designs, which meet all NTV circuit design requirements are further investigated. These SPC FFs are designed for NTV operation in TSMC 65LP and compared against the classic transmission gate FF (TGFF). Celllevel design issues and variation are explored in the context of a 5000 gate AES encryption macro. Key design issues are identified, which erode the claimed benefits of SPC FFs when implemented as part of a larger design. We conclude that aggressive reduction in FF clock loading offers benefits but can lead to functional failures when OCV is considered, especially at NTV. Given the theoretical benefits of SPC FFs for enabling IoT, the need for further work on SPC FF designs is highlighted.

5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability

RC Relaxation Oscillators (RxO) are attractive for integrated clock sources compared to LC and ring oscillators (RO), as LC oscillators pose integration challenges and RO designs have limited voltage and temperature (V-T) stability. RxOs generate a clock whose time period (TP) depends only on the timing resistor (R) and capacitor (C). Ideally, TP is independent of V-T; however, most RxOs use a reference voltage (VREF) against which the voltage of C (Vc) is compared. Generating a V-T-independent VREF is non-trivial and causes variations in RxO frequency. A common approach is the use of VDD-independent current sources or band-gap or device-Vt-based VREF [1]. The former are generally high-power options [2] while the latter is subject to process and V-T variations. A correct-by-design approach was adopted in [3] demonstrating VDD-independent operation by cancelling variations through differential sampling of VDD. Further, the power overhead of a supply-independent VREF is overcome by exploiting differential-integrator virtual ground. However, 4V2/R power in the RC tank and high-power VCO increase the energy/cycle.

A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems

Small, low-cost and energy efficient wireless sensor nodes (WSNs) form a vital part of the Internet of Things (IoT). WSNs spend the majority of their time in low-power sleep mode and wake up for short intervals. To ensure minimum energy (MinE) operation of such sensor nodes, fast wide-range voltage scaling is required. As voltage is aggressively scaled between ultra-low retention levels and sub, near or super-threshold active levels, monitoring circuits become essential to guarantee safe operation of the system. This work demonstrates a 50nW voltage monitor fabricated as part of the power management unit (PMU) of a 65nm MinE WSN. Ultra low power operation is achieved by duty-cycling the comparators. Further, dynamic power-bandwidth balancing results in lower quiescent power without loss of response speed. Measured results show 6µs response time giving a superior power-delay balance compared to prior works. This paper describes the design, implementation and measured results along with system implications of the design choices.