Tom J. Kazmierski

Accurate Supercapacitor Modeling for Energy Harvesting Wireless Sensor Nodes

Supercapacitors are often used in energy harvesting wireless sensor nodes (EH-WSNs) to store harvested energy. Until now, research into the use of supercapacitors in EH-WSNs has considered them to be ideal or oversimplified, with non-ideal behavior attributed to substantial leakage currents. In this brief, we show that observations previously attributed to leakage are predominantly due to redistribution of charge inside the supercapacitor. We confirm this hypothesis through the development of a circuit-based model, which accurately represents non-ideal behavior. The model correlates well with practical validations representing the operation of an EH-WSN and allows behavior to be simulated over long periods.

Numerically Efficient Modeling of CNT Transistors With Ballistic and Nonballistic Effects for Circuit Simulation

This paper presents an efficient carbon nanotube (CNT) transistor modeling technique that is based on cubic spline approximation of the nonequilibrium mobile charge density. The approximation facilitates the solution of the self-consistent voltage equation in a CNT so that calculation of the CNT drain-source current is accelerated by at least two orders of magnitude. A salient feature of the proposed technique is its ability to incorporate both ballistic and nonballistic transport effects without a significant computational cost. The proposed models have been extensively validated against reported CNT ballistic and nonballistic transport theories and experimental results.

A Dual-Gate Graphene FET Model for Circuit Simulation—SPICE Implementation

This paper presents a SPICE compatible model of a dual-gate bilayer graphene field-effect transistor. The model describes the functionality of the transistor in all the regions of operation for both hole and electron conduction. We present closed-form analytical equations that define the boundary points between the regions to ensure Jacobian continuity for efficient circuit simulator implementation. A saturation displacement current is proposed to model the drain current when the channel becomes ambipolar. The model proposes a quantum capacitance that varies with the surface potential. The model has been implemented in Berkeley SPICE-3, and it shows a good agreement against experimental data with the normalized root-mean-square error less than

Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density

10\%

An integrated approach to energy harvester modeling and performance optimization

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Timeless Discretization of Magnetization Slope in the Modeling of Ferromagnetic Hysteresis

This paper presents a new carbon nanotube transistor (CNT) modelling technique which is based on an efficient numerical piece-wise non-linear approximation of the non-equilibrium mobile charge density. The technique facilitates the solution of the self-consistent voltage equation in a carbon nanotube such that the CNT drain-source current evaluation is accelerated by more than three orders of magnitude while maintaining high modelling accuracy. The model is currently limited to ballistic transport but can be extended to non-ballistic modes of transport when a suitable theory is developed while researchers study phenomena that sometimes prevent electrons in a carbon nanotube from going ballistic. Our results show that while the accuracy and speed of the proposed model vary with the number of piece-wise segments in the mobile charge approximation, it is possible to obtain a speed-up of more than 1000 times while maintaining the accuracy within less than 2% in terms of average RMS error compared with the state of the art theoretical reference CNT model implemented in FETToy. This numerical efficiency makes our model particularly suitable for implementation in circuit-level, eg. SPICE-like, simulators where large numbers of such devices may be used to build complex circuits.

Behavioral modelling of RF filters in VHDL-AMS for automated architectural and parametric optimization

This paper proposes an integrated approach to energy harvester (EH) modeling and performance optimization where the complete mixed physical-domain EH (micro generator, voltage booster, storage element and load) can be modeled and optimized. We show that electrical equivalent models of the micro generator are inadequate for accurate prediction of the voltage boosters performance. Through the use of hardware description language (HDL) we demonstrate that modeling the micro generator with analytical equations in the mechanical and magnetic domains provide an accurate model which has been validated in practice. Another key feature of the integrated approach is that it facilitates the incorporation of performance enhanced optimization, which as will be demonstrated is necessary due to the mechanical-electrical interactions of an EH. A case study of a state-of-the-art vibration-based electromagnetic EH has been presented. We show that performance optimization can increase the energy harvesting rate by about 40%.

Multilayer Graphene FET Compact Circuit-Level Model With Temperature Effects

A new methodology is presented to assure numerically reliable integration of the magnetization slope in the Jiles-Atherton model of ferromagnetic core hysteresis. Two hardware description language (HDL) implementations of the technique are presented: one in SystemC and the other in very-high-speed integrated circuit (VHSIC) HDL (VHDL) analog and mixed signal (AMS). The new model uses timeless discretization of the magnetization slope equation and provides superior accuracy and numerical stability especially at the discontinuity points that occur in hysteresis. Numerical integration of the magnetization slope is carried out by the model itself rather than by the underlying analog solver. The robustness of the model is demonstrated by practical simulations of examples involving both major and minor hysteresis loops

An efficient and accurate MEMS accelerometer model with sense finger dynamics for applications in mixed-technology control loops

This contribution presents a methodology, based on VHDL-AMS modelling, for architectural and parametric optimization of high-frequency analogue filters, used in the process of automated synthesis. The synthesis methodology has been designed around the usage of VHDL-AMS parse trees as an intermediate system representation. Behavioral description of filters combines the familiar mathematical/numerical expressions which contain the vital design parameters of an analogue filter such as the quality factor and frequency range. The user specification is processed by the filter synthesis tool named FIST which produces a selection of analogue filter circuits that are suitable for integrated high-frequency applications.

An automated design flow for vibration-based energy harvester systems

This paper presents a circuit-level model of a dual-gate bilayer and four-layer graphene field effect transistor. The model provides an accurate estimation of the conductance at the charge neutrality point (CNP). At the CNP, the device has its maximum resistance, at which the model is validated against experimental data of the device off-current for a range of electric fields perpendicular to the channel. The model shows a good agreement for validations carried out at constant and varying temperatures. Using the general Schottky equation, the model estimates the amount of bandgap opening created by the application of an electric field. Also, the model shows good agreement when validated against experiment for the channel output conductance against varying gate voltage for both a bilayer and four-layer graphene channel.