Anant Shankar Kamath

Aging Precursor Identification and Lifetime Estimation for Thermally Aged Discrete Package Silicon Power Switches

Thermal/power cycles are widely acknowledged methods to accelerate the package related failures. Many studies have focused on one particular aging precursor at a time and continuously monitored it using custom-built circuits. Due to the difficulties in taking sensitive measurements, the reported findings are more on the quantities requiring less sensitive measurements. In this paper, two custom-designed testbeds are used to age a number of power MOSFETs and insulated gate bipolar transistors. An automated curve tracer is utilized to capture parametric variations in I–V curves, parasitic capacitances, and gate charges at certain time intervals. The results suggest that the only viable aging precursors are the on-state voltage drop/on-state resistance, body diode voltage drop, parasitic capacitances, and gate threshold voltage for die attach solder and gate-oxide degradation mechanisms. Based on the experimental results, gate threshold voltage variation is empirically modeled to estimate the remaining useful lifetime of the switches experiencing gate oxide degradation. The model parameters are found by the least squares method applied to inliers determined by the random sample and consensus outlier removal algorithm.

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented.

A 1.8GHz Digital PLL in 65nm CMOS

A 1.8GHz high-accuracy, ring-oscillator based Digital Phase Lock Loop (DPLL), suitable for Serializer-Deserializer (SERDES) applications like HDMI, eSATA and USB2.0 is presented here. Sigma-Delta (??) dithering followed by passive filtering, along with Temperature Compensation is used to ensure frequency accuracy and low accumulated jitter, over a large temperature range. A re-circulating delay line based Time to Digital Converter (T2D) is used to handle large phase differences between the reference and feedback clocks. The DPLL is built in 65nm technology, and provides up to 1.8GHz output, with a phase noise of –87dBc/Hz at 1 MHz offset, and a frequency accuracy of +/-100ppm. It supports input frequencies in the range 0.7MHz to 50MHz, occupies a core area of 0.11 sq mm, and does not require external components.

A 13MHz input, 480MHz output Fractional Phase Lock Loop with 1MHz bandwidth

A 13MHz input, 480MHz output Fractional Phase Lock Loop (PLL), having 1MHz bandwidth, is presented here. To handle the non-integer feedback divider ratio (480/13), a novel approach is chosen. A Delay Lock Loop (DLL) is used to generate 13 phases of the 480MHz VCO clock; one of these phases is multiplexed to an integer mode feedback divider; every reference cycle the multiplexer shifts to the adjacent phase, resulting in the period of the feedback clock, after the divider, being 1/13th of a VCO clock period short of an integer multiple. This results in an effective fractional division. The Phase Detector (PD) does not see any phase errors due to this operation; hence no additional filtering is required in the loop. The loop bandwidth can therefore be maintained to a value as high as one tenth of the reference clock, in contrast to other popular fractional PLL schemes. The affect of the DLL to the PLL loop stability and jitter is analyzed and found to be non significant. The PLL can be re-configured to also support 15.36MHz and 16.8MHz in fractional mode, and 20MHz, 19.2MHz, 12MHz, 24MHz and 48MHz in integer mode, while always maintaining high bandwidth. The PLL is designed and simulated in 90nm CMOS. It occupies an area of 0.1 sq mm, and does not require off-chip components.

A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0

A high accuracy, ring-oscillator based Digital Phase Lock Loop (DPLL), suitable for USB2.0 application, is presented here. The Digitally Controlled Oscillator (DCO) of the DPLL consists of a current mode Digital to Analog Converter (DAC) combined with a Current Controlled Oscillator (ICO). Sigma- Delta (ΣΔ) dithering is used on the DAC for improved frequency accuracy. To reduce noise due to ΣΔ dithering and to allow for passive filtering of this noise, the ΣΔ section of the DAC is limited to a small range. This range, however, is not sufficient to account for frequency drifts due to temperature: a novel temperature compensation scheme is used for this purpose. The DPLL is built in 65nm technology, and provides a 480MHz output, with a phase noise of −103.5dBc/Hz at 1 MHz offset, and a frequency accuracy of +/-100ppm. It supports a list of input frequencies: 13MHz, 12MHz, 19.2MHz, 24MHz and 48MHz, occupies a die area of 0.21 sq mm, and does not require external components.

A current mode 2.4 GHz direct conversion receiver

A novel direct-conversion RF architecture is proposed that has a current mode interface between the low noise amplifier (LNA) and the down-conversion mixer, as well as the mixer and the base-band filter. The proposed architecture eliminates the voltage swing at the output of all the radiofrequency blocks. The voltage swing is seen only in the baseband after second order filtering, thus resulting in significant linearity improvements and robustness to adjacent channel interference. The current mode interface between filter and mixer also eliminates a redundant voltage-current conversion, giving significant noise advantages. A prototype wireless local area network (WLAN) receiver was designed and simulated in 0.13 /spl mu/m technology, giving a third-order input-referred intercept point of 5 dBm and a noise figure of 2.7 dB for the receive chain. The circuit (including base-band) consumes 8 mA from a 1.2 V supply.

A wide output range, mismatch tolerant Sigma Delta DAC for digital PLL in 90nm CMOS

A mismatch-tolerant current-mode Sigma Delta (ΣΔ) Digital to Analog Converter (DAC) is presented here. The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought out for separate ΣΔ operation. This increases the DAC range even as the ΣΔ step size and range are kept small to minimize ΣΔ switching noise. Mismatch between DAC current elements can result in Differential Non Linearity (DNL) at the DAC output. A novel scheme is proposed to mitigate this effect. It involves skewing the thresholds of the quantizer in the ΣΔ modulator based on the DAC input, in order to control which DAC elements are used in generating a particular output current. The DAC, implemented as part of a Digital PLL in 90nm CMOS, yields a current range of up to 2mA and occupies an area of 0.035mm2. It is shown that the proposed scheme attenuates mismatch effects by a factor of 16.

Slew-rate controlled 800Mbps transmitter in 65nm CMOS

A slew-rate controlled, 800Mbps voltage mode differential transmitter is presented here. An add-on, capacitive charge transfer based scheme is used to control output rise/fall times. The transmitter, designed and fabricated in a 65nm CMOS technology, occupies an active area of 0.02mm2 and consumes 2.7mW. Of this, the add-on slew-rate control occupies an area of 0.0027mm2, and consumes 0.5mW.

4×2Gbps Source-Synchronous Transmitter in 45nm CMOS

A 4-lane, 2Gbps-per-lane, source synchronous, voltage-mode differential transmitter is presented here. Staggered switching of driver termination is used to obtain controlled, nearlinear rise/fall transitions on the pads. The timing for the staggering is generated by a calibrated digitally controlled delay line. An on-chip high bandwidth regulator serves as a low impedance 400mV source required for voltage mode transmission. The transmitter, designed and fabricated in 45nm CMOS technology, occupies a core area of 0.013mm2 per lane and consumes 4.3mW/Gbps.

A 2GHz Digital PLL, with temperature lock range of −40°C to 125°C, in 45nm CMOS

A 2GHz, ring-oscillator based Digital PLL (DPLL) with temperature lock range of −40°C to 125°C is presented here. The Digitally Controlled Oscillator (DCO) of the DPLL consists of a current mode Digital to Analog Converter (DAC) followed by a Current Controlled Oscillator (ICO). The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought out for separate ΣΔ operation. This increases the DAC range and hence the DPLL temperature lock range, even as the ΣΔ step size and range are kept small to minimize jitter. The DPLL achieves a phase noise of −90dBC/Hz at 1MHz offset for 2GHz operation. It supports an input frequency range of 0.5MHz to 50MHz, occupies a core area of 0.09mm2 and consumes 7.2mW.