Karthik Subburaj

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented.

Spur Mitigation in High-Sensitivity GNSS Receivers

The presence of spurious tones in a Global Navigation Satellite Signal (GNSS) receivers RF and analog front-end signal spectrum leads it to compute receivers position erroneously. Addressing spurs is crucial in modern multiconstellation GNSS receivers as their wide bandwidth and coexistence on a shared chip or board with other radios and processors make them highly susceptible to corruption by dynamically varying spurs. Proposed here is a solution to mitigate a large number of spurs in GNSS receivers using a combination of limited number of frequency-tracked digital hardware filters, fast Fourier transform-based spur detectors, and a firmware algorithm predicting and weeding out potentially corrupt satellite measurements. Laboratory validation results from an experimental GNSS receiver in a CMOS system-on-chip are shown to demonstrate its effectiveness.

Highly-linear FM transmitter for mobile application in 65nm CMOS

An FM frequency synthesizer and antenna driver with >63dB SNR, <0.1% THD, and −dBc out-of-band emissions at 124dBµV output swing in 65nm digital CMOS is described. The optimized FLL incorporates a DCO with a highly linear capacitor array and flicker noise reduction techniques. Cascaded filtering and a segmented driver improve efficiency and tuning range with minimal high-order distortion.

A 300 KBPS 23.2 MHz Binary Frequency Shift Keying Transmitter for USB Power Line Communication in 180 nm BiCMOS

A Binary Frequency Shift Keying transmitter particularly suited for the recently introduced USB Power Delivery standard is presented here. The proposed architecture uses a combination of intelligent frequency planning, an unmodulated high frequency PLL, a digital clock rate converter, and a sine-weighted DAC impedance matched to the power-line network. This combination simultaneously achieves frequency keying and output signal generation in a novel highly integrated way. It achieves a Figure of Merit and a data-rate-normalized energy efficiency better than or comparable to generic Direct Digital Synthesis architectures and previously published FSK designs, at a fraction of their die area. Details of its architecture and implementation, 180 nm BiCMOS measurement results, and comparison with best existing designs are presented.

Techniques to enhance GNSS signal acquisition and tracking sensitivity

Enhancing GNSS acquisition and tracking sensitivity is critical to improving the GNSS user experience in indoor situations. This paper describes various techniques to enhance GNSS signal acquisition and tracking sensitivity and increasing the robustness and availability of position fixes. Specifically, a technique called Staggered Coherent Integration is proposed which enables up to 1 dB improvement in sensitivity compared to conventional techniques. Also discussed are challenges in tracking the weak signals seen in indoor conditions and techniques to improve sustained tracking under these conditions. Analysis and simulation results are shown to demonstrate the effectiveness of the techniques described.

A 2GHz Digital PLL, with temperature lock range of −40°C to 125°C, in 45nm CMOS

A 2GHz, ring-oscillator based Digital PLL (DPLL) with temperature lock range of −40°C to 125°C is presented here. The Digitally Controlled Oscillator (DCO) of the DPLL consists of a current mode Digital to Analog Converter (DAC) followed by a Current Controlled Oscillator (ICO). The current mode DAC is designed such that the outputs of any two adjacent current elements can be progressively brought out for separate ΣΔ operation. This increases the DAC range and hence the DPLL temperature lock range, even as the ΣΔ step size and range are kept small to minimize jitter. The DPLL achieves a phase noise of −90dBC/Hz at 1MHz offset for 2GHz operation. It supports an input frequency range of 0.5MHz to 50MHz, occupies a core area of 0.09mm2 and consumes 7.2mW.