Gopalkrishna Ullal Nayak

Architectures and Circuit Techniques for Multi-Purpose Digital Phase Lock Loops

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented.

A 1.8GHz Digital PLL in 65nm CMOS

A 1.8GHz high-accuracy, ring-oscillator based Digital Phase Lock Loop (DPLL), suitable for Serializer-Deserializer (SERDES) applications like HDMI, eSATA and USB2.0 is presented here. Sigma-Delta (??) dithering followed by passive filtering, along with Temperature Compensation is used to ensure frequency accuracy and low accumulated jitter, over a large temperature range. A re-circulating delay line based Time to Digital Converter (T2D) is used to handle large phase differences between the reference and feedback clocks. The DPLL is built in 65nm technology, and provides up to 1.8GHz output, with a phase noise of –87dBc/Hz at 1 MHz offset, and a frequency accuracy of +/-100ppm. It supports input frequencies in the range 0.7MHz to 50MHz, occupies a core area of 0.11 sq mm, and does not require external components.

A 65nm CMOS, ring-oscillator based, high accuracy Digital Phase Lock Loop for USB2.0

A high accuracy, ring-oscillator based Digital Phase Lock Loop (DPLL), suitable for USB2.0 application, is presented here. The Digitally Controlled Oscillator (DCO) of the DPLL consists of a current mode Digital to Analog Converter (DAC) combined with a Current Controlled Oscillator (ICO). Sigma- Delta (ΣΔ) dithering is used on the DAC for improved frequency accuracy. To reduce noise due to ΣΔ dithering and to allow for passive filtering of this noise, the ΣΔ section of the DAC is limited to a small range. This range, however, is not sufficient to account for frequency drifts due to temperature: a novel temperature compensation scheme is used for this purpose. The DPLL is built in 65nm technology, and provides a 480MHz output, with a phase noise of −103.5dBc/Hz at 1 MHz offset, and a frequency accuracy of +/-100ppm. It supports a list of input frequencies: 13MHz, 12MHz, 19.2MHz, 24MHz and 48MHz, occupies a die area of 0.21 sq mm, and does not require external components.

A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS

A 0.5-4GHz fractional-N phase locked loop (PLL) capable of spread-spectrum clock (SSC) generation in low leakage 28nm CMOS process is presented. A novel technique of bandwidth control enables the PLL to be used for clocking multi-protocol SERDES PHYs. The PLL has a voltage controlled ring oscillator and achieves a phase noise of-86dBc/Hz at 1MHz offset for 4GHz operation. It supports an input frequency range of 10MHz to 100MHz, occupies an area of 0.092mm2 and consumes 9.56mW power.